AM437x Low Power Suspend Mode with LPDDR2


Design files


This low power mode implementation realizes processor power consumption less than 0.1 mW while keeping LPDDR2 memory in self refresh consuming ~ 1.6 mW. The system solution is comprised of AM437x Sitara processor, LPDDR2 memory and TPS65218 power management IC and optimized for new low power mode along with support for legacy low power modes. The processor power is minimized by turning off all the processor power supplies except RTC power supply. System power state transitions including power supply control can be performed by single interface signal (PMIC_PWR_EN signal) with PMIC register programming.

  • Suspend to RAM with the lowest system power mode
    • AM437x in RTC-only mode
    • TPS65218 in suspend state
    • LPDDR2 in self refresh
  • System can resume back to the state it was before suspending
  • RTC-only suspend power consumption
    • AM43x + TPS65218: < 0.1 mW
    • Typical 2Gb LPDDR2: 1.6 mW
  • Suspend Events by:
    • By programming RTC registers
    • By setting up the RTC alarm
  • Resume Events:
    • RTC alarm goes off
    • PMIC push button or AC power detection
  • Resume Time
    • < 300 msec hardware latency
    • < 1 sec for software to resume to previous state (depending on application use case)
  • This design is tested and includes schematics, BOM, and design guide.
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU571.PDF (56 K)

Reference design overview and verified performance test data


Detailed schematic diagram for design layout and components


Complete listing of design components, reference designators, and manufacturers/part numbers


Files used for 3D models or 2D drawings of IC components


Includes TI products in the design and potential alternatives.

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Technical documentation

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Type Title Date
Design guide AM437x Low-Power Suspend Mode With LPDDR2 Design Guide Oct. 03, 2014

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