CDCLVC1310-EVM
CDCLVC1310 評估模組
CDCLVC1310-EVM
概覽
The CDCLVC1310 is a highly versatile, low jitter and low power clock fan out buffer, which distributes up to ten low jitter LVCMOS clock outputs. The clock is derived from one of three inputs, whose primary and secondary inputs feature differential or single-ended signals and the third input is a crystal input.
特點
- Easy-to-use evaluation board to fan out low phase-noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at 2.5-/3.3-V for VDD and at 1.5-/1.8-/2.5-/3.3-V for VDDO
- Single-ended or differential input clocks or crystal input
時鐘緩衝器
技術文件
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| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| 證書 | CDCLVC1310-EVM EU Declaration of Conformity (DoC) | 2019/1/2 | ||||
| 使用指南 | 10-Output Low Jitter Low Power Differential to LVCMOS Clock Buffer - Evaluation | 2011/11/29 |