CDCLVP1102EVM
CDCLVP1102 評估模組
CDCLVP1102EVM
概覽
The CDCLVP1102 is a high-performance, low additive phase noise clock buffer. It has a single universal input buffer that supports either single-ended or differential clock inputs, and feeds to two LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP1102. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP1102 device functionalities. For optimum performance, the board is equipped with 50-W SMA connectors and well-controlled, 50-W impedance microstrip transmission lines.
特點
- Easy-to-use evaluation board to fan out low phase noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at +2.5-/+3.3-V
- Single-ended or differential input clocks
- CDCLVP1102 supports two LVPECL outputs; CDCLVP1102EVM supports one LVPECL output
時鐘緩衝器
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| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | EVM User's guide | CDCLVP1102EVM User's Guide | 2009/7/9 | |||
| 證書 | CDCLVP1102EVM EU Declaration of Conformity (DoC) | 2019/1/2 |