CDCLVP2106EVM
CDCLVP2106 評估模組
CDCLVP2106EVM
概覽
The CDCLVP2106 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock input. Each input feeds a bank of six LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP2106. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP2106device functionalities. For optimum performance, the board is equipped with 50-ohm SMA connectors and well-controlled, 50-ohmimpedance microstrip transmission lines.
特點
- Easy-to-use evaluation board to fan out low phase noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at +2.5-V/+3.3-V
- Single-ended or differential input clocks
- CDCLVP2106 supports 12 LVPECL outputs; CDCLVP2106EVM supports four LVPECL outputs
時鐘緩衝器
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| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | EVM User's guide | Low Additive Phase Noise Clock Buffer Evaluation Board | 2009/8/25 | |||
| 證書 | CDCLVP2106EVM EU Declaration of Conformity (DoC) | 2019/1/2 |