TIDEP0018
適用於 Sitara 處理器的平行攝影機介面
TIDEP0018
概覽
This camera interface design connects to a 10-bit parallel interface to the AM335x general purpose memory controller (GPMC) 16-bit multiplexed address/data bus. This design consumes roughly 150mW less power than typical USB solutions, and is ideal for applications like portable data terminals, ruggedized handhelds, portable consumer, industrial handhelds and others. The reference design is based on the QuickLogic 3.1 MP Camera Sensor (using an Aptina 3.1 MP sensor) connected to a camera expansion board. Together, they connect to the BeagleBone platform. The BeagleBone and the QuickLogic 3.1 MP camera add-on board are available for purchase.
More information on QuickLogic: http://www.quicklogic.com
More information about BeagleBone: https://www.ti.com/tool/beaglebn
More information about the QuickLogic 3.1 MP camera add-on board for the BeagleBone, including design files and software: http://www.quicklogic.com/solutions/reference-designs/ti-sitara-beaglebone-camera-cape/
特點
- Supports up to 5MP camera at 10fps with DMA
- Up to 30 frames per second (fps) at VGA (640 x 480) resolution
- Reduces system power consumption up to 150mW
- No software effort required for OEM
- 6x6mm, non-HDI rules package
- This is an example sub-system design that includes schematics, BOM, Gerbers and other design files.
已開發完全組裝的電路板，僅供測試與性能驗證，且為非賣品。
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產品
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技術文件
| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 設計指南 | Parallel Camera Interface for Sitara Processors Design Guide | 2014/7/29 | |||
| Third party document | Low Power Camera Interface to BeagleBone Reference Design [QuickLogic Information Page] | 2014/7/30 | ||||
| Third party document | BeagleBone 3.1MP Camera Cape System Reference Manual | 2014/7/30 |