TIDEP0037
使用 TMS320C6678 處理器實作具電源效率且可擴充的 H.265/HEVC 解決方案參考設計
TIDEP0037
概覽
HEVC is an efficient, but processing intensive video standard, that is said to double the data compression ratio compared to H.264 / MPEG-4 at the same level of video quality. This design shows how a power efficient, soft H.265 / HEVC solution, that scales across resolutions, frame rates & profiles, can be implemented in real time using one or more TMS320C6678 devices. A specific use case of a single channel HEVC 720p30 real time encoder and single channel HEVC 1080p60 real time decoder is also included. TI’s HEVC C66x HEVC encoder shows a bitrate saving, for the same visual quality, of greater than 40% compared with TI’s H.264 x encoder. TMS320C66x DSPs support both audio and video codecs.
特點
- The TIDEP0037 reference design is tested, and includes a hardware reference (EVM), software and a user's guide.
- TMDSEVM6678 EVM for a high performance, cost-efficient, standalone development platform, using the TMS320C6678 high-performance DSP based on TI's C66x Keystone multicore architecture.
- This design includes schematics, design files, and a bill of materials.
- HEVC/ H.265 encoder and decoder, MCSDK framework and other software packages
- Design guide discusses performance and scalability across DSP cores and devices to achieve desired HEVC configuration
已開發完全組裝的電路板，僅供測試與性能驗證，且為非賣品。
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技術文件
| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 設計指南 | Using TMS320C6678 to Implement H.265/HEVC Design Guide (Rev. A) | 2015/10/19 |