TIPD142
DAC 取樣保持降干擾參考設計
TIPD142
概覽
DAC R-2R architectures display great performance in regards to noise and accuracy, but at a cost of large glitch area. This design focuses on the reduction of major-carry glitches that occur from code specific transitions in DAC R-2R architectures. This design reduces this glitch area, making it suitable for glitch-sensitive applications such as waveform generation.
特點
- 18-bit, 0-5 V output
- R-2R DAC with S&H Glitch Reduction Circuitry
- <0.015 %FSR total unadjusted error
- <2 LSB INL
已開發完全組裝的電路板，僅供測試與性能驗證，且為非賣品。
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| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| 使用指南 | Sample & Hold Glitch Reduction for Precision Outputs Design Guide | 2013/12/10 |