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Hi, I am Prasana. In this video, I will introduce you to a subsystem called PRU-ICSS, in the Sitara family of processors. In particular, I'll show you how PRU-ICSS can be used for connecting the processor with multiple ADCs instead of an FPGA.

Let's look at the setup. We have four boards here. A sensor board, an AFE board, a BeagleBone Black EVM, and an interface board. The sensor board is used to connect to the secondary site of PT and CT. The output is connected to an analog front end card with six data converters and gain and driver stage. The output of this is connected to BeagleBone Black EVM board through the interface card.

Now, let's look at the block diagram. On the left, you will see six ADCs with eight channels each or 48 channels in total. Each ADC runs at 256 kSPS. On the right is the Sitara processor. The GPIOs from the PRU subsystem on the left connects to all the six ADCs.

Each PRU has two cores. The first core connects to the Aspire interface of ADC and controls the timing and synchronization of ADCs independently. The second core is used for processing the data captured. With the combination we will estimate the signal frequency in core one and change the sampling rate in core zero.

There are three key benefits. Increased ADC throughput. The PRU-ICSS independently controls the timing on the ADC interface. The spire and the data base are not tied up, resulting in significantly higher throughput. Freeing up of processor. The processor no longer has to manage resource allocation, thereby freeing up of its bandwidth. Improved data acquisition performance. Coherent sampling is implemented using core one and core zero of PRU-ICSS to minimize spectral leakages.

For more information, please visit the link below, or search for TIDA-01555 on ti.com. Thanks for watching this video.

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