Hello. My name is Richard Herring, Applications Engineer with HPD at TI. This presentation is on gate drive considerations for low frequency and DC operation.

Here's a little bit on my background. I went to school at Texas A&M University. I have over 20 years power conversion experience in computing, telecom, and embedded power electronics.

Since at TI, I have systems and applications engineering experience with flyback controllers, LED lighting, and high power gate drivers.

Half bridge gate drivers are used in a variety of low frequency applications. This topic will cover half bridge gate driver considerations, specifically the high side floating gate drive in low frequency and DC versions. We'll cover typical low frequency apps, concerns for the floating high side bias and design guidance.

Be sure and check out the HPD gate drivers page on TI.com.

We'll cover the following topics, starting with some typical applications of low frequency half bridge drivers.

A common application for half bridge drivers is the inductive heater. The major blocks include the EMI filter, PFC stage, and DC to AC inverter driving the inductive coil.

In this example is a full bridge converter stage with the isolation and the power transformer. You can see that the inverter bridge requires a high side floating drive for the high side power devices. The inverter drives a resonant load to maximize the current in its heater coil.

Some of these applications operate at switching frequencies of around 2 kilohertz.

Another common application for half bridge gate drivers is a motor drive for a variety of end products. Major blocks include the EMI filter, PFC stage, and DC to AC inverter.

In this example, the totem pole PFC is shown along with a three phase motor drive inverter. You can see there are six high side power devices that require floating high side driver. VFDs can operate at low frequency, and have long on times during speed reduction and braking.

In the diagram of the boot-strap bias for the high side driver, you can see the boot diode is connected to the VDD and HB pin. The HB capacitor charges when the HS goes low.

When the LO driver goes high, the HS node goes low, which provides the charging path for the HB capacitor.

The HB capacitor charging current is sourced from the VDD capacitor.

Both the VDD and HB bias have UVLO delays. HS must go low for the HB capacitor to charge. In most cases, LO must switch for the HS to go low.

In the timing diagram, here's a typical half bridge startup sequence. You can see that the low side switches before the HB to HS bias rises. And there is an HB UVLO delay before the HO can switch.

High voltage half bridge drivers utilize an edge triggered level shifter. The benefits of this are low cost for high voltage level shift and reduce power dissipation versus a DC or a high frequency modulated level shifter.

Shown here is the edge triggered level shifter and pulse filter.

TI drivers provide a robust level shifter function. We have a 70 nanosecond pulse coupled with a 14 nanosecond pulse filter to improve the noise humidity. Also, there is a fairly high pulse trigger current at 6 milliamps. It's also improved the dV/dt immunity.

This signals is HI input signal after UVLO and dead time logic. These two signals are the rising edge level shifter pulse and the falling edge pulse generator.

There are some additional considerations for the half bridge driver startup sequence specific to the edge triggered level shifter.

The HB to HS bias must be above the UVLO threshold and the UVLO delay. Also, the HB to HS bias must be beyond the UVLO delay on the rising edge of the HI to trigger HO.

This sequence shows the timing of the HB UVLO delay expiring before the rising edge of HI. You can see that the UVLO delay was over before the turn on pulse to the level shifter.

In this timing example, you can see the rising edge happen before the UVLO delay, and the HO did not respond. After the HB UVLO delay, the next rising will result in an HO response.

This is an example of the high side bias capacitor charging and discharging. C BOOT is charged during the low side on time. This example represents a low duty cycle for the low side switch.

The HB to HS capacitor charged from VDDs to the boot diode when the HS switch is close to ground. The HB-HS capacitors is discharged from the following; charging a MOSFET QG, also, the gate driver HP quiescent current, and any gate to source leakage.

Avoid low value gate to source resistors, as this can significantly impact the HB bias discharge during long HO on times.

Here we're going to review the process to determine the minimum boot strap capacitor value.

First, determine the allowable HB to HS delta V based on VDD and VHB UVLO or the minimum target VGS voltage.

Determine the total charge required from the MOSFET total charge, or QG, and the HB to HS quiescent current and leakage currents.

From these results, you can determine the minimum C BOOT value.

Let's look in an example to calculate C BOOT. We'll look at the UCC27712 driver, and an ST 26 amp, 60 volt MOSFET, and initially assume a gate to source resistance of 20 K-ohms.

The VDD is 12 volt. VDF is 0.6. And we'll target the VGS minimum of 10 volts in this example. This results in a 1.4 volt allowable VHB drop.

With a switching frequency of 2 kilohertz, you can see that the Q TOTAL is impacted quite a bit over QG by the IBL leakage, IQBS quiescent current, and current from RGS.

The calculated min C BOOT is 260 nanofarad per 2 kilohertz, and then HO 90% duty cycle.

With 100 Hertz switching frequency, the Q total increases considerably.

This results in the C BOOT min of 4.3 microfarad.

Notice the significance of the current from RGS. RGS should only be sized to take care of MOSFET leakage currents, not within the expectation of Miller current during the switch node rising TBDT, as the gate driver can keep the output low during these conditions.

The VDD capacitor is recommended to be about 10 times the boot capacitor value. This is to minimize the VDD discharge during C BOOT charging. Use high frequency X7R capacitance in parallel with the bulk capacitance.

The boot diode should be fast recovery and low capacitance to avoid discharging of the HP capacitor. The boot resistance range is typically in the 2.2 to 10 ohm range, and is determined by a VDD and the boot diode peak current rating.

For DC or long HO on times, C BOOT cannot be realistically sized to sustain the HB bias.

And the isolated floating bias is needed for HB to HS. The TI SN6501, or 6505, is a very simple solution. There are small off-the-shelf transformers available from Wurth Electronics, and there are various voltage and isolation configurations available.

Make sure in this case that you place an X7R cap with a value high enough to support the MOSFET QG close to the driver. You can see the links for the SN6501 and the available transformers from Wurth Electronics.

There's a TI reference design for a high voltage motor driver for automotive HVAC compressor. Check out the TIDA-01418 on TI.com.

For lower voltage motor drives, such as 48 volt automotive or portable battery tools, the TI 100 to 120 volt bridge drivers, such as the LM5109B, and six intervolt drivers, including the 27710 and the UCC27712, are well-suited for these applications.

Thank you for your time.