This demo configures TimerG in compare mode to build a hardware frequency divider. PA12 detects edges of PB0's 50%-duty square wave which frequency adjustable via UART. TIMG auto-counts edges and triggers interrupt when counts match the target value, such as input_freq for 1s period. Jumper links PB0 to PA12, while REPEAT COUNTER suppresses intermediate interrupts, achieving zero-CPU-load pulse processing.