12.1 Layout Guidelines

Employ best design practices when laying out a printed circuit board (PCB) for both analog and digital components. Best design practice is to separate analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog multiplexers] from noise generating digital components [such as microcontrollers and switching regulators]. An example of good component placement is shown in Figure 73. Although Figure 73 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any high-resolution analog components.

Figure 73. System Component Placement Example

The following outlines some basic recommendations for the layout of the ADS1257 to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.

• Separate analog and digital signals. Partition the board into analog and digital sections when the layout permits. Route digital lines away from analog lines to help prevent digital noise from coupling into analog signals.
• Avoid splitting analog and digital ground planes. When possible, use a single solid ground plane for both analog and digital signals. A low impedance connection between AGND and DGND with minimal voltage difference between the ADS1257 analog and digital ground pins (AGND and DGND) is essential for optimum performance. If the system employs split digital and analog ground planes, connect the ground planes together as close to the device as possible.
• Fill void areas on signal layers with ground fill.
• Provide good ground return paths. Signal return currents follow the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing adjacent to the signal trace, the current finds another path to return the source. If forced onto a longer path, the return current increases the possibility that the signal radiates or interferes with other sensitive circuitry.
• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. For best results, place the bypass capacitors on the same layer and as close to the active device as possible.
• Consider the resistance and inductance of the routing. Large resistance on the input traces can react with the input bias current and cause an added offset voltage. Reduce loop areas enclosed by the source signal and the return current in order to reduce input inductance and help prevent EMI pickup.
• Route all differential signal traces as matched differential pairs. When possible, use adjacent analog inputs, such as AIN0, AIN1 and AIN2, AIN3, for differential measurements.
• Analog inputs with differential connections must have a differential filtering capacitor placed across the inputs. Use high-quality differential capacitors, such as C0G (NPO) dielectric capacitors, that have stable properties and low-noise characteristics.

12.2 Layout Example

Figure 74 shows an example layout for the ADS1257 with a four layer PCB (only three layers are visible).

Figure 74. Four-Layer PCB Layout Example

Analog and digital grounds share a ground plane. Do not place other traces are placed on the ground plane layer. Multiple parallel vias are used to reduce ground connection impedance and connect ground planes on multiple layers. Analog and digital signals are partitioned into separate areas on the PCB (as if a ground split was made) to reduce the potential for digital noise to couple into the analog signals. Where possible, ground plane fill is used on all layers.

Supply and reference signals are shown as traces routed on the top layer; however, these signals can also be provided to the ADS1257 through an internal layer. For best performance, the negative reference signal (REFN) must be routed back to the reference source with a trace and connected to ground near the reference source, to prevent ground plane currents from coupling into this signal. Route signal traces as differential pairs to minimize noise pick-up from adjacent traces.

Digital signals with fast rise and fall times are subject to ringing and overshoot if not properly terminated. Series resistors placed near the driving source terminate the transmission line of the PCB trace and suppress voltage ringing. When routing digital signals, give priority to CLKIN and SCLK signals. Keep clock traces as short as possible, routed directly above a ground plane, and routed with a minimum number of vias. GPIOs and control signal traces with slower edges and less frequent switching (such as D0, CS, SYNC/PWDN, and RESET) are not as sensitive to layout and can be made longer and use additional vias to make room for more critical digital signals (such as CLKIN, SCLK, DIN, and DOUT). Note that when multiple ADS1257s are used, the external clock signal can be routed to CLKIN on one device, and then serially connected from CLKOUT to CLKIN on the next device to simplify layout.