SBAS533D March   2011  – December 2015 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. ADS424x/422x Family Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 8.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 8.7  Electrical Characteristics: General
    8. 8.8  Digital Characteristics
    9. 8.9  Timing Requirements: LVDS and CMOS Modes
    10. 8.10 Serial Interface Timing Characteristics
    11. 8.11 Reset Timing (Only When Serial Interface Is Used)
    12. 8.12 Typical Characteristics
      1. 8.12.1 ADS4246
      2. 8.12.2 ADS4245
      3. 8.12.3 ADS4242
      4. 8.12.4 ADS4226
      5. 8.12.5 ADS4225
      6. 8.12.6 ADS4222
      7. 8.12.7 General
      8. 8.12.8 Contour
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
        1. 9.3.1.1 Drive Circuit Requirements
        2. 9.3.1.2 Driving Circuit
      2. 9.3.2 Clock Input
      3. 9.3.3 Digital Functions
      4. 9.3.4 Gain for SFDR/SNR Trade-off
      5. 9.3.5 Offset Correction
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down
        1. 9.4.1.1 Global Power-Down
        2. 9.4.1.2 Channel Standby
        3. 9.4.1.3 Input Clock Stop
    5. 9.5 Programming
      1. 9.5.1 Parallel Configuration Only
      2. 9.5.2 Serial Interface Configuration Only
      3. 9.5.3 Using Both Serial Interface and Parallel Controls
      4. 9.5.4 Parallel Configuration Details
      5. 9.5.5 Serial Interface Details
        1. 9.5.5.1 Register Initialization
        2. 9.5.5.2 Serial Register Readout
      6. 9.5.6 Digital Output Information
        1. 9.5.6.1 Output Interface
        2. 9.5.6.2 DDR LVDS Outputs
        3. 9.5.6.3 LVDS Buffer
        4. 9.5.6.4 Parallel CMOS Interface
        5. 9.5.6.5 CMOS Interface Power Dissipation
        6. 9.5.6.6 Multiplexed Mode of Operation
        7. 9.5.6.7 Output Data Format
    6. 9.6 Register Maps
      1. 9.6.1 Description Of Serial Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Analog Input
        2. 10.2.2.2 Clock Driver
        3. 10.2.2.3 Digital Interface
        4. 10.2.2.4 SNR and Clock Jitter
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Sharing DRVDD and AVDD Supplies
    2. 11.2 Using DC/DC Power Supplies
    3. 11.3 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Grounding
      2. 12.1.2 Supply Decoupling
      3. 12.1.3 Exposed Pad
      4. 12.1.4 Routing Analog Inputs
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Ultralow Power With Single 1.8-V Supply, CMOS Output:
    • 183 mW Total Power at 65 MSPS
    • 277 mW Total Power at 125 MSPS
    • 332 mW Total Power at 160 MSPS
  • High Dynamic Performance:
    • 88-dBc SFDR at 170 MHz
    • 71.4-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V parallel CMOS Interface
    • Double Data Rate (DDR) LVDS With Programmable swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude Down to
    200 mVPP
  • Package: VQFN-64 (9.00 mm × 9.00 mm)

2 Applications

  • Wireless Communications Infrastructure
  • Software-Defined Radio
  • Power Amplifier Linearization

3 Description

The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit/12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS4222 VQFN (48) 9.00 mm × 9.00 mm
ADS4225
ADS4226
ADS4242
ADS4245
ADS4246
  1. For all available packages, see the orderable addendum at the end of the data sheet.

ADS4222/25/26/42/45/46 Block Diagram

ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246 fbd_424x_bas533.gif