9.3.1 Low-Noise Amplifier (LNA)

The analog input signal is buffered and amplified by an on-chip LNA. LNA gain is programmable with the LNA_GAIN register, as shown in Table 6.

The LNA output is internally limited to 2 V_PP. Thus, the maximum-supported input peak-to-peak swing is set by 2 V / LNA_GAIN_Linear.

Input-referred noise in default mode is 2.9 nV/√Hz at 30-dB PGA gain and 15-dB LNA gain. Input-referred noise can be further improved to 2.5 nV/√Hz by enabling the HIGH_POW_LNA register bit. However, this noise reduction results in increased power dissipation.

9.3.2 Programmable Gain Amplifier (PGA)

The PGA amplifies the analog input signal by a programmable gain. Gain can be programmed using the PGA_GAIN register, common to all channels, in 3-dB steps with a gain range of 30 dB. In default mode, PGA gain ranges from 0 dB to 30 dB. In equalizer mode, PGA gain ranges from 15 dB to 45 dB. PGA_GAIN register settings are listed in Table 7. Figure 57 shows the typical SNR values across PGA gain.

Figure 57. SNR Across PGA Gain

9.3.3 Antialiasing Filter

The device introduces a third-order, elliptic, active, antialias, low-pass filter (LPF) in the analog signal path. The filter –3-dB corner frequency can be configured using the FILTER_BW register, as shown in Table 8. The corresponding frequency response plots are shown in Figure 58 and Figure 59.

Figure 58. Filter Response Across Modes
(PGA Gain = 0 dB)

Figure 59. Filter Response Across Modes
(PGA Gain = 30 dB)

9.3.4 Analog-to-Digital Converter (ADC)

The filtered analog input signal is sampled and converted into a digital equivalent code using a high-speed, low-power, 12-bit, pipeline ADC. The digital output of the device has a latency of 10.5 t_{AFE_CLK} cycles because of the pipeline nature of the ADC. The digitized output of the device is in binary twos complement (BTC) format. The output format can be changed to offset binary format with the OFF_BIN_DATA_FMT register bit.

9.3.5 Digital Gain

The ADC output can be incremented digitally using a digital gain block. Digital gain is common for all channels and can be configured by enabling MULT_EN and applying the desired DIG_GAIN. Channel gain is given by Equation 1:

Equation 1.

where

• (DIG_GAIN + 32) is the mod 128 number.

Figure 60 shows the typical digital gain curve for different DIG_GAIN values.

Figure 60. Digital Gain Graph

9.3.6 Input Clock Divider

The device clock input is passed through a clock divider block that can divide the input clock by a factor of 1, 2, 3, or 4. This divided clock (AFE_CLK) is used for simultaneously sampling the four ADC inputs. In default mode, a division factor of 1 is used where the AFE_CLK frequency is the same as the input clock frequency. The clock divider block can be enabled using the DIV_EN register bit and, when enabling this bit, the AFE_CLK frequency is automatically determined by the serialization factor set by the CH_OUT_DIS register bits (Table 12). The division factor can also be manually specified by enabling the DIV_FRC and DIV_REG register bits. Care must be taken to ensure that the input clock frequency is within the recommended operating range specified in the Recommended Operating Conditions.

After device reset, the divider is reset at the first pulse applied on the TRIG pin. This configuration is especially useful when using multiple devices in the system, where the sampling instants of all ADCs in the system must be synchronized. Figure 61 illustrates the TRIG timing diagram and the various divided-down AFE_CLK signals. Figure 62 provides the TRIG input setup and hold time with respect to the device clock input. Bit settings for the DIV_EN register, DIV_FRD register, and DIV_REG register are provided in Table 9, Table 10, and Table 11, respectively.

Figure 61. Input Clock Divider

Figure 62. TRIG CLKIN Setup and Hold

9.3.7 Data Output Serialization

The input signals are digitized by the dedicated channel ADCs. Digitized signals are multiplexed and output on D[11:0] as parallel data.

The output data rate and the DCLK speed are automatically calculated based on the CH_OUT_DIS[1:4] bits. The number of zeroes in these four bits is equal to the serialization factor for the output data. When the register bit is set to 1, the output for the respective channel is disabled. The channels are arranged in ascending order, with the lowest active channel output first and the highest active channel output last. CH_OUT_DIS[1:4] controls only the output serialization and does not power-down individual channels. Table 12 lists the register values with the respective serialization factors and output sequence.

9.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs

9.3.8.1 Main Channels

The device analog input consists of a differential LNA. The common-mode for the LNA inputs is internally set using two internal, programmable, single-ended resistors, as shown in Figure 63.

Figure 63. Common-Mode Biasing of LNA Input Pins

These resistors can be programmed to a higher value using the TERM_INT_20K_LNA register setting as described in Table 13.

Table 13. Internal Termination Register Setting (LNA)

TERM_INT_20K_LNA	DESCRIPTION
0	RINTTERM_LNA = 1 kΩ
1	RINTTERM_LNA = 10 kΩ

Hence, for proper operation, the input signal must be ac-coupled. Note that external input ac-coupling capacitors form a high-pass filter (HPF) with RINT_{TERM_LNA}. Therefore, the capacitor values should allow the lowest frequency of interest to pass with minimum attenuation. For typical frequencies greater than 1 MHz, a value of 50 nF or greater is recommended. The maximum input swing is limited by the LNA gain setting. LNA output swing is limited to 2 V_PP before the output becomes saturated or distorted.

Single ended mode of operation is also possible by connecting non-driven input pin to ground through a capacitor of 100 nF. However, this will result in reduced linearity.

9.3.8.2 Auxiliary Channel

The auxiliary analog inputs (IN_IP_AUX, IN_IM _AUX) can be enabled instead of the IN_IP, IN_IM inputs using the AUX_CH_I_EN bits (Table 14). The auxiliary analog input signal path consists of an input unity-gain buffer followed by an ADC. The LNA, PGA, equalizer, and antialiasing filter are bypassed and powered down in this mode. Figure 64 shows the internal block diagram for auxiliary channel mode. When this mode is enabled, the maximum input swing is limited to 2 V_PP before the input becomes saturated or distorted.

Table 14. AUX_CH_I_EN Register

AUX_CHI_EN	DESCRIPTION
0	INIP, INIM active, analog
1	INIP _AUX, INIM_AUX

NOTE:

Dashed area denotes one of four channels.

Figure 64. Common-Mode Biasing of Auxiliary Channel Input Pins

The dc common-mode on the IN_IP_AUX, IN_IM _AUX pins are internally biased to the optimum voltage (referred to as VCM).

The dc common-mode biasing is set with two internal, programmable, single-ended resistors (RINT_{TERM_AUX}). These resistors can be programmed to a higher value using the TERM_INT_20K_AUX register setting as described in Table 15.

Table 15. Internal Termination Register Setting (AUX)

TERM_INT_20K_AUX	DESCRIPTION
0	RINTTERM_AUX = 1 kΩ
1	RINTTERM_AUX = 10 kΩ

The auxiliary inputs can also be ac-coupled as a result of the internal common-mode setting. The external input ac-coupling capacitors form a high-pass filter with RINT_{TERM_AUX}. Therefore, the capacitor values should allow the lowest frequency of interest to pass with minimum attenuation.

For typical frequencies greater than 1 MHz, a value of 50 nF or greater is recommended. For instances where the input signal cannot be ac-coupled because of system requirements, it is recommended to use the VCM output to set the dc common-mode of the input signal. The driving capability of VCM is limited. A 100-nF capacitor should be connected on each VCM input to AVSS.

9.4.1 Equalizer Mode

In some applications, the input signal power linearly decreases with signal frequency. Such types of input spectrum can be equalized using a first-order signal equalizer. The device can be configured in two different equalizer modes: EQ_EN and EQ_EN_LOW_FC. Table 16 lists the register settings for these modes.

• EQ_EN mode: In this mode, a high-pass filter (HPF) is added to the analog signal path between the LNA output and PGA input.
• EQ_EN_LOW_FC mode: In this mode, attenuation from the HPF is limited to unity in the pass-band frequency range.

The HPF and LPF cutoff frequencies (of the antialiasing filter) are the same as per the FILTER_BW setting. In this mode, overall channel gain increases by an additional fixed gain of 15 dB from the HPF block. Typical frequency response plots showing different equalizer modes along with the default mode are shown in Figure 65 and Figure 66.

Figure 65. Filter Response (PGA Gain = 0 dB)

Figure 66. Filter Response (PGA Gain = 30 dB)

9.4.2 Data Output Mode

The functionality of DSYNC1, DSYNC2, DCLK, and D[11:0] are controlled by selecting the data output mode. The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins for 4x serialization modes are shown in Figure 67 and Figure 68. Any event on the TRIG pin triggers the DSYNC1 and DSYNC2 signals. The DSYNC1 period is determined by the COMP_DSYNC1 register value and the DSYNC2 period is determined by the SAMPLE_COUNT register value. When OUT_MODE_EN = 0, data output is continuous. When OUT_MODE_EN = 1, data is active only during the sample phase. Output pins are configured using the registers described in Table 17 through Table 21.

Figure 67. Data Output Timing Diagram (4x Serialization)

Figure 68. Data Output Timing Diagram (4x Serialization, Input Divider Enabled)

The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins with the input divider enabled for 3x serializations is shown in Figure 69.

Figure 69. Data Output Timing (3x Serialization, Input Divider Enabled)

The TRIG to DSYNC2 latency is given by Table 22.

9.4.2.1 Header

Each channel has an associated 12-bit header register. These registers can be written by an SPI write. The content of this register can be read out on the CMOS data output (D[11:0]) by configuring the HEADER_MODE register, as shown in Table 23.

Table 23. HEADER_MODE Register

HEADER_MODE	DESCRIPTION
0	ADC data at output
1	Header data at output
2	[Temperature data, diagnostic data, mean, noise, (-1), (-1), (-1), (-1)]. This data sequence is repeated.
3	Header data, temperature data, diagnostic data, mean, noise, ADC data

In HEADER_MODE = 3, the header mode data output is shown in Figure 70.

In this mode, header data is transmitted with a latency with respect to the TRIG input. This latency is given by Equation 2:

Equation 2. TRIG to Header Latency (T_{TRIG_HEADER_LAT}) = t_{AFE_CLK} + T_{TRIG_DSYNC2_LAT}

Figure 70. Header Mode Data Output (HEADER_MODE = 3)

9.4.3 Parity

Parity for each output sample of an active channel can be read on the D_GPO[1:0] pins by configuring these pins with the DGPO1_MODE, DGPO0_MODE register, as shown in Table 25. Parity generation can be enabled using the D_GPO_EN bit, as shown in Table 26. The type of parity generation can be configured to odd or even based on the PARITY_ODD bit, as shown in Table 27.

9.4.4 Standby, Power-Down Mode

The device can be put into standby mode with the STDBY register bit. In this mode, all blocks except the ADC reference blocks are powered down. In GLOBAL_PDN mode, all blocks including the ADC reference blocks are powered down. However, in both modes, the serial interface is active.

9.4.5 Digital Filtering to Improve Stop-Band Attenuation

The device introduces a standard 11-tap, symmetric finite impulse response (FIR) digital filter for additional stop-band attenuation in decimate-by-2 and decimate-by-4 modes. In both modes, the FIR digital filter coefficients (C1 to C6) must be configured to obtain the desired filter characteristics. However, set 1 coefficients are loaded by default at device reset.

In this mode, device power consumption increases and the DSYNC period scales according to the decimation mode (the DSYNC period increases by 2x in decimate-by-2 mode and 4x in decimate-by-4 mode when compared to normal mode). Maximum AFE_CLK frequency supported in the decimation modes is 50 MHz.

9.4.5.1 Decimate-by-2 Mode

In this mode, the DECIMATE_2_EN and FILT_EN register bits must be set, and the filter coefficients should be configured. Figure 71 shows typical filter response in decimate-by-2 mode for the filter coefficient of set 1 (default). Note that the output data rate is reduced by a factor of 2 as compared to default mode for the given clock input frequency.

Figure 71. Decimate-by-2 Filter Response (f_S = 50 MHz)

9.4.5.2 Decimate-by-4 Mode

In this mode, the DECIMATE_2_EN, DECIMATE_4_EN, and FILT_EN register bits must be set, and the filter coefficients should be configured. Figure 72 shows a typical filter response in decimate-by-4 mode for the filter coefficient of set 1 (default) and set 2. Note that the output data rate is reduced by a factor of 4 as compared to default mode for the given clock input frequency.

1.

NOINDENT:

Set 1: C1 = 5, C2 = 2, C3 = –13, C4 = –2, C5 = 38, and C6 = 66. Set 2: C1 = –5, C2 = –2, C3 = 7, C4 = 19, C5 = 30, and C6 = 34.

Figure 72. Decimate-by-4 Filter Response (f_S = 12.5 MHz)1

9.4.6 Diagnostic Mode

The device offers various diagnostic modes to check proper device operation at a system level. These modes can be enabled using the SPI and the outputs of these modes are stored in diagnostic read-only registers.

1. Internal reference status check: In this mode, the on-chip band-gap voltage, ADC reference, and clock generation are verified for functionality. Reading a 0 on these bits indicates that these blocks are functioning properly. The DIAG_MODE_EN register bit must be set to 1. The DIG_REG register bits for this mode are:
   • DIG_REG[0] for ADC references,
   • DIG_REG[1] for band gap, and
   • DIG_REG[2] for clock generation.
2. DC input force: In this mode, a dc voltage can be internally forced at the LNA input to test the entire signal chain. During this test, the device analog inputs should be left floating. This mode can be asserted by setting the DC_INP_EN bit to 1 and programming the DC_INP_PROG[0:2] bits. In this mode, the equalizer is disabled internally.
3. Variance (noise) and mean measurement: Variance and mean of the ADC output can be analyzed using the on-chip STAT module. The STAT_EN, STAT_CALC_CYCLE, and STAT_CH_SEL, STAT_CH_AUTO_SEL options should be set to compute the variance and mean. These values can be monitored using channel-specific, read-only registers. Alternatively, these values can also be read using HEADER_MODE. Output variance and mean calculation is determined by Equation 3.
Equation 3.

STAT_CALC_CYCLE must be set to a large value to obtain better accuracy. Mean provides the average dc value of the ADC output (mid code). The STAT module integration time is defined by: t_{AFE_CLK} × 2^{(STAT_CALC_CYCLE+1)} when the STAT_CH_SEL option is selected. When STAT_CH_AUTO_SEL is enabled, the STAT module integration time is defined by: 4 × t_{AFE_CLK} × 2^{(STAT_CALC_CYCLE+1)}.

4. Temperature sensor: The device junction temperature measurement can be enabled and monitored using TEMP_SENS_EN and TEMP_CONV_EN. The temperature output is saved in a diagnostic read-only register, TEMP_DATA. Alternatively, this data can also be read using HEADER_MODE. The TEMP_DATA value is a 9-bit, twos complement data in degrees Celsius. The temperature data is internally updated as per Equation 4:
Equation 4. Temperature Data Update Cycle = 1024 × T_{AFE_CLK} × 16

9.4.7 Signal Chain Probe

To enhance system-level debug capabilities, the device offers a mode where the output of each block in the signal chain can be connected to the ADC input. With this mode, internal signals can be easily monitored to ensure that each block output is not saturated. Figure 73 shows the device signal chain block diagram. Figure 74 and Figure 75 show typical frequency response plots at the output of each stage.

Figure 73. Signal Chain Block Diagram

Figure 74. Frequency Response for
VOUT_ON_ADC Settings (PGA Gain = 0 dB)

Figure 75. Frequency Response for
VOUT_ON_ADC Settings (PGA Gain = 30 dB)

9.5.1 Serial Interface

Different modes can be programmed through the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET pins. SCLK and SDATA have a 150-kΩ pull-down resistor to ground and SEN has a 150-kΩ pull-up resistor to DVDD18. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data bits are latched at every SCLK rising edge when SEN is active (low). Serial data bits are loaded into the register at every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data bits can be loaded in multiples of 24-bit words within a single active SEN pulse (an internal counter counts groups of 24 clocks after the SEN falling edge). The interface can function with SCLK frequencies from 20 MHz down to very low speeds and even with a non-50% duty-cycle SCLK. Data bits are divided into two main portions: a register address (8 bits, A[7:0]) and data (16 bits, D[15:0]).

9.5.2 Register Initialization

After power up, the internal registers must be initialized to the default value (0). Initialization can be accomplished in one of two ways:

• Either through a hardware reset, by applying a positive pulse to the RESET pin, or
• Through a software reset with the serial interface, by setting the SW_RST bit high. Setting this bit initializes the internal registers to the respective default values (all 0s) and then self-resets the SW_RST bit low. In this case, the RESET pin can stay low (inactive).

During a register write through the SPI, the effects on data propagate through the pipe while the internal registers change values. At the same time, some glitches may be present on the output because of the transition of register values (for instance, if any output-controlling modes change). The signal on the RESET pin must be low in order to write to the internal registers because reset is level-sensitive and asynchronous with the input clock. Although only 40 ns are required after the RESET rising edge to change the registers, the output data may take up to 20 clock cycles (worst-case) to be considered stable. For more information on RESET, see the Timing Requirements: RESET.

9.5.2.1 Register Write Mode

In register write mode, the REG_READ_EN bit must be set to 0. In this mode, the SDOUT signal outputs 0. Figure 76 shows this process.

Figure 76. Serial Interface Register Write

9.5.2.2 Register Read Mode

In register readout mode, the REG_READ_EN bit must be set to 1. Then, a serial interface cycle should be initiated, specifying the address of the register (A[7:0]) whose content must be read out of the device. The data bits are don’t care. The device outputs the contents (D[15:0]) of the selected register on the SDOUT pin. The external controller latches the data on SDOUT at the SCLK rising edge. Figure 77 shows this process.

The timing specifications for the serial interface operation is listed in the Timing Requirements: Serial Interface Operation.

Figure 77. Serial Interface Register Readout Enable

9.5.3 CMOS Output Interface

The digital data from the four channels are multiplexed and output over a 12-bit parallel CMOS bus to reduce the device pin count. In addition to the data, a CMOS clock (DCLK) is also output, which can be used by the digital receiver to latch the AFE output data. The output data and clock buffers can typically drive a 5-pF load capacitance in default mode. To drive larger loads (10 pF to 15 pF), the strength of the CMOS output buffers can be increased using the STR_CTRL_CLK and STR_CTRL_DATA register bits. Note that the setup and hold time of the output data (with respect to DCLK) degrade with higher load capacitances. See Table 1, which provides timings for 5-pF and 15-pF load capacitances.

9.5.3.1 Synchronization and Triggering

While the digital data from the four channels is multiplexed on the output bus, some mechanism is required to identify the data from the individual channels. Other than the output data and DCLK, the device also outputs DSYNCx signals that can be used for channel identification.

The DSYNCx output signals function with the TRIG input signal. Every time that a trigger pulse is received on the TRIG pin, the device outputs the DSYNC1 and DSYNC2 signals. The DSYNCx signals can be configured in the following ways:

• The delay between the arrival of the TRIG signal and the DSYNCx signal becoming active is programmable in a number of AFE_CLK cycles (using the DELAY_COUNT register bit).
• The period of the DSYNC1 signal is programmable in terms of AFE_CLK clock cycles by using the COMP_DSYNC1 register bits.
• The active time of the DSYNC2 signal is programmable using the SAMPLE_COUNT register bits.

The rising edge of the DSYNC1 signal coincides with the channel 1 data, as shown in Figure 78. This occurrence can be used by the receiving device to identify individual channels.

The sample phase period corresponds to the period when valid data is available from the device when OUT_MODE_EN = 1.

Figure 78. DSYNCx Timing Diagram

9.6.1 Functional Register Map

Table 28 shows the register map for the AFE5401 registers.

9.6.2 Register Descriptions

Bits 15:8	C2_FIR: Coefficient C2 for FIR digital filter (1)
	2 = Default value
Bit 7:0	DIG_GAIN_C1_FIR: Digital Gain common for all channels, coefficient C1 for decimation filter
	Equation 5. where (DIG_GAIN + 32) is Mod(2) 128. Refer to Figure 60 for more information.
	Mode	C1 Functionality
	With MULT_EN	DIG_GAIN
	With DECIMATE_X _EN	Coefficient C1 for FIR digital filter
	5 = Default value