SBAS475A June   2009  – January 2023 AMC6821-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 ADC Converter
      2. 8.2.2 Temperature Sensor
        1. 8.2.2.1 Series Resistance Cancellation
        2. 8.2.2.2 Reading Temperature Data
        3. 8.2.2.3 Temperature Out-of-Range Detection
        4. 8.2.2.4 Remote Temperature Sensor Failure Detection
      3. 8.2.3 PWM Output
      4. 8.2.4 PWM Waveform Setting
      5. 8.2.5 Fan Speed Measurement
        1. 8.2.5.1 Tach-Data Register
          1. 8.2.5.1.1 Reading the Tach Data Register
          2. 8.2.5.1.2 RPM Measurement Rate
          3. 8.2.5.1.3 Select Number of Pulses/Revolution
          4. 8.2.5.1.4 Tach Mode Selection
          5. 8.2.5.1.5 Fan RPM Out-of-Range Detection
      6. 8.2.6 Fan Failure Detection
      7. 8.2.7 FAN-FAULT Pin
      8. 8.2.8 Fan Control
        1. 8.2.8.1 THERM Pin and External Hardware Control
          1. 8.2.8.1.1 THERM Pin as an Output
          2. 8.2.8.1.2 THERM Pin as an Input
        2. 8.2.8.2 Fan Spin-Up
        3. 8.2.8.3 Normal Fan Speed Control
          1. 8.2.8.3.1 Software DCY Control Mode
          2. 8.2.8.3.2 Software-RPM Control Mode (Fan Speed Regulator)
          3. 8.2.8.3.3 Auto Temperature Fan Mode
      9. 8.2.9 Interrupt
        1. 8.2.9.1 OVR Pin
        2. 8.2.9.2 SMBALERT Pin
        3. 8.2.9.3 SMBALERT Interrupt Behavior
        4. 8.2.9.4 Handling SMBALERT Interrupts
    3. 8.3 Device Functional Modes
    4. 8.4 Programming
      1. 8.4.1 SMBus Interface
        1. 8.4.1.1 Communication Protocols
      2. 8.4.2 SMBus Alert Response Address (ARA)
      3. 8.4.3 Power-On Reset and Start Operation
    5. 8.5 Register Map
      1. 8.5.1 Register Description
        1. 8.5.1.1 Device Configuration Registers
        2. 8.5.1.2 Device Status Registers
        3. 8.5.1.3 Fan Controller Registers
        4. 8.5.1.4 Temperature Data Registers
        5. 8.5.1.5 Temperature Limit Registers
          1. 8.5.1.5.1 Tach-Data Register
          2. 8.5.1.5.2 Tach Setting Register
          3. 8.5.1.5.3 Tach Low Limit Register
          4. 8.5.1.5.4 Tach High Limit Register
  9. 9 Application and Implementation
    1. 9.1 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1.1 Device Configuration Registers

Table 8-14 Configuration Register 1 (Address 0x00, Value After Power-On Reset = 0xD4)
BITNAMER/WDEFAULTDESCRIPTION
7THERMOVIER/W1THERM interrupt enable. When this bit is set, the THERM interrupt is enabled. L-THERM = 1 or R-THERM = 1 causes an interrupt. When this bit is cleared ('0'), the THERM interrupt is disabled. When disabled, L-THERM = 1 or R-THERM = 1 does not assert the SMBALERT pin, but forces the THERM pin low. Power-on default = 1.
6FDRC1R/W1Fan driver control bit 1. Power-on default = 1. Refer to Table 8-15.
5FDRC0R/W0Fan driver control bit 0. Power-on default = 0. Refer to Table 8-15.
4FAN-Fault-ENR/W1Setting this pin to '1' enables the FAN-FAULT pin. Clearing this pin ('0') disables the FAN-FAULT pin (always in Hi-Z). Power-on default = 1.
3PWMINVR/W0PWM invert bit. When PWMINV = 0 (default), the PWM-Out pin goes low for 100% duty cycle (suitable for driving the fan using a PMOS device). Setting PWMINV to '1' makes the PWM-Out pin go high (with an external pull-up resistor) for 100% duty cycle (suitable for driving the fan using a NMOS device). Power-on default = 0.
2FANIER/W1Fan RPM interrupt enable bit. Power-on default = 1. When FANIE = 1, the FAN-RPM interrupt is enabled. FANS = 1 or RPM-ALARM = 1 generates a FANORN interrupt, making the SMBALERT pin go low. When FANIE = 0, a FAN-RPM interrupt is disabled. Fan out-of-range = 1 does not generate an interrupt.
1INT-ENR/W0Setting this bit to '1' enables the interrupt from the SMBALERT pin. Clearing this bit ('0') disables the interrupt. Power-on default = 0.
0STARTR/W0Temperature monitoring and fan speed monitoring. When START = 0 , only software-DCY control mode works; software-RPM and auto temperature control modes do not work.
Table 8-15 Fan Driver Control Bits
FDRC1FDRC0FUNCTION
11Maximum speed calculated control. The required duty cycle for remote temperature and local temperature is calculated respectively. The larger value is used to control the fan.
10Auto remote-temperature-fan control. The PWM duty cycle is controlled by the remote temperature. Power-on default mode.
00Software DCY control. Host writes DCY register to set the PWM duty cycle directly.
01Software RPM control. Host writes the TACH setting register with the value corresponding to the desired RPM. The device measures the actual RPM and adjusts the PWM duty cycle to maintain the fan speed to the target value.
Table 8-16 Configuration Register 2 (Address 0x01, Value After Power-On Reset = 0x3D)
BITNAMER/WDEFAULTDESCRIPTION
7RSTR/W0Reset bits. RST = 1 resets the device. Self-clears after reset. Always read '0'. Power-on default = 0. Reset is immediate on rising edge of SCLK of data LSB with no acknowledge.
6PSVIER/W0LPSV enable bit. Power-on default = 0. When LPSVIE = 1, the LPSV interrupt is enabled and an interrupt is generated when LPSV = 1. When LPSVIE = 0, LPSV is disabled and LPSV = 1 does not cause an interrupt.
5RTOIER/W1Remote temperature interrupt enable bit. When RTIE = 1, the remote temperature interrupt is enabled and RTO = 1 causes an interrupt. When RTIE = 0, the remote temperature interrupt is disabled and RTO = 1 does not generate an interrupt. Power-on default = 1, except when a remote sensor failure is detected at power-on.
4LTOIER/W1Local temperature interrupt enable bit. Power-on default = 1. When LTIE = 1, the local temperature interrupt is enabled and LTO = 1 causes an interrupt. When LTIE = 0, the local temperature interrupt is disabled and LTO = 1 does not generate an interrupt.
3RTFIER/W1Remote sensor failure interrupt enable bit. Power-on default = 1. When RTFIE = 1, the remote sensor failure interrupt is enabled and RTF = 1 causes an interrupt through the SMBALERT pin. When RTFIE = 0, the remote sensor failure interrupt is disabled and RTF = 1 does not generate an interrupt through the SMBALERT pin.
2TACH-ENR/W1Setting this bit to '1' enables the TACH input. Clearing ('0') disables the TACH input and freezes the counter. Power-on default = 1. If TACH-EN is cleared, TACH-MODE must be set ('1').
1TACH-MODER/W0When the TACH-MODE bit is cleared ('0'), the PWM-Out pin is forced ON during RPM measurement, and internal correction circuitry is enabled to correct the error caused by this extra duty cycle. Making TACH-MODE = 0 for the fans that are switched ON/OFF directly by the PWM requires PWM ON to provide TACH pulses. In the software RPM mode, the PWM-Out is forced to 30% duty cycle if the calculated duty cycle is less than 30% when TACH-MODE = 0. In all other modes the PWM-Out is forced to 0% if the calculated duty cycle is less than 7%. When the TACH mode is set ('1'), the internal correction circuit is disabled and PWM-Out is not forced ON. Instead, the PWM-Out pin is completely controlled by the value of the DCY register, just as in normal operation. Setting the TACH-MODE bit ('1') when the fans can provide TACH pulses output regardless the status of the PWM-Out pin. The TACH mode must be '1' for any fan which is powered directly by dc power, such as a four-wire fan. Power-on default = 0. (See the TACH-DATA Register section for details.)
0PWM-ENR/W1Setting this bit to '1' enables the PWM-Out pin. Clearing ('0') disables the PWM-Out pin (H-Z). Power-on default = 1.
Table 8-17 Configuration Register 3 (Address 0x3F, Value After Power-On Reset = 0x82)
BITNAMER/WDEFAULTDESCRIPTION
7THERM-FAN-ENR/W1Setting this bit to '1' enables the fan to run at full-speed when the THERM pin as an output) is asserted low. This configuration allows the system to be run in performance mode. Clearing this bit to '0' disables the fan from running at full-speed whenever the THERM pin (as an output) is asserted low. This configuration allows the system to run in silent mode. Note that this bit has no effect whenever THERM is pulled low as an input. The fan always runs at full speed when the THERM pin is pulled low as an input. Power-on default = 1.
6ReservedR0Read-back '0'.
5ReservedR0Read-back '0'.
4ReservedR0Read-back '0'.
3Part Revision NumberR00, bit 3 (MSB) of 4-bit revision number.
2Part Revision NumberR00, bit 2 of revision number.
1Part Revision NumberR10, bit 1 of revision number.
0Part Revision NumberR00, bit 0 (LSB) of revision number.
Table 8-18 Configuration Register 4 (Address 0x04, Value After Power-On Reset = 0x08)
BITNAMER/WDEFAULTDESCRIPTION
7MODER/W0Required configure bit: User must write a 1 to this location.
6PSPRR/W0Number of pulses per revolution of the fan. Power-on default = 0. PLSPR = 0 for two pulses/revolution (default), PLSPR = 1 for four pulses per revolution.
5TACH-FASTR/W0When TACH-FAST = 1, the TACH data reading is updated every 250ms. This monitor is the fast RPM monitor. When TACH-FAST = 0, the TACH data reading is updated every second. Default = 0, power-on default = 0.
4OVRENR/W0Setting this bit to '1' enables the OVR pin. Clearing this bit ('0') disables the OVR pin (high-impedance). Default = 0.
3ReservedR1Read back '1'.
2ReservedR0Read-back '0'.
1ReservedR0Read-back '0'.
0ReservedR0Read-back '0'.

Writing the reserved bit has no effect.