SBOS559B May   2011  – October 2015 AMC80

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Block Level Description
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 Default Interrupt Mode
        2. 7.3.2.2 One-Time Interrupt Mode
        3. 7.3.2.3 Comparator Mode
      3. 7.3.3 Interrupt Structure
    4. 7.4 Programming
      1. 7.4.1 Interface and Control
    5. 7.5 Register Map
      1. 7.5.1  Configuration Register
      2. 7.5.2  Interrupt Status Registers
      3. 7.5.3  Interrupt Mask Registers
      4. 7.5.4  Fan Divisor/RST_OUT/OS Register
      5. 7.5.5  OS Configuration/Temperature Resolution Register
      6. 7.5.6  Conversion Rate Register
      7. 7.5.7  Voltage/Temperature Channel Disable Register
      8. 7.5.8  Input Mode Register
      9. 7.5.9  ADC Control Register
      10. 7.5.10 Conversion Rate Count Register
      11. 7.5.11 Value Ram Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Power-On
      2. 8.1.2 Analog Inputs
      3. 8.1.3 Fan Inputs
  9. 9 Device and Documentation Support
    1. 9.1 Community Resources
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
AMC80 po_bos559.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NO. NAME
1 INT_IN Input Digital Interrupt input pin. An active low input that extends the INT_IN signal to the INT output of the AMC80.
2 SDA I/O Digital Serial bus data line for SMBus, open-drain; requires pull-up resistor.
3 SCL I/O Digital Serial bus clock line for SMBus, open-drain; requires pull-up resistor.
4 FAN1 Input Digital Fan tachometer input pin
5 FAN2 Input Digital Fan tachometer input pin
6 BTI Input Digital Board temperature interrupt pin. BTI is driven by the over-temperature shutdown (OS) outputs of the additional temperature sensors. This pin has an internal 10-kΩ pull-up resistor.
7 GPI(CI) Input Digital General-purpose input pin (chassis interrupt). An active high interrupt input pin to latch a chassis interrupt event.
8 DGND Power Analog Digital ground.
9 V+ Power Analog Positive supply voltage (3V to 5.5V).
10 INT Output Digital Non-maskable interrupt (active high, PMOS, push-pull) or interrupt request (active low, NMOS, push-pull) pin. The INT pin becomes active when INT_IN, BTI, or GPI interrupts. This pin does not require a pullup resistor to V+.
11 GPO Output Digital General-purpose output pin. GPO is an active low, NMOS, open-drain output. This pin is intended to drive an external power PMOS for software power control or to control power to a cooling fan.
12 NTEST_IN/RESET_IN Input Digital This pin is an active-low input that enables NAND tree board-level connectivity testing. The AMC80 resets to its power-on state when NAND tree connectivity is enabled.
13 RST_OUT/OS Output Digital This pin is an NMOS open-drain output. RST_OUT provides a master reset to devices connected to this line. OS is dedicated to the temperature reading alarm.
14 AGND Power Analog Analog ground. This pin must be tied to a low-noise analog ground plane for optimum performance.
15 CH6 Input Analog Analog input channel 6
16 CH5 Input Analog Analog input channel 5
17 CH4 Input Analog Analog input channel 4
18 CH3 Input Analog Analog input channel 3
19 CH2 Input Analog Analog input channel 2
20 CH1 Input Analog Analog input channel 1
21 CH0 Input Analog Analog input channel 0
22 A0/NTEST_OUT I/O Digital The lowest order bit of the serial bus address. During a NAND tree test for ATE board-level connectivity, this pin functions as an output.
23 A1 Input Digital Address pin 1
24 A2 Input Digital Address pin 2