SLUSBY5G June   2014  – December 2015

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  High Impedance Mode
      2. 7.4.2  Battery Only Connected
      3. 7.4.3  Input Connected
        1. 7.4.3.1 Input Voltage Protection in Charge Mode
          1. 7.4.3.1.1 Sleep Mode
          2. 7.4.3.1.2 Input Voltage Based Dynamic Power Management (VIN-DPM)
          3. 7.4.3.1.3 Input Overvoltage Protection
        2. 7.4.3.2 Charge Profile
      4. 7.4.4  Battery Charging Process
      5. 7.4.5  Charge Time Optimizer
      6. 7.4.6  Battery Detection
      7. 7.4.7  Battery Overvoltage Protection (BOVP)
      8. 7.4.8  Dynamic Power Path Management
      9. 7.4.9  Battery Discharge FET (BGATE)
      10. 7.4.10 IUSB1, IUSB2, and IUSB3 Input
      11. 7.4.11 Safety Timer in Charge Mode
      12. 7.4.12 LDO Output (DRV)
      13. 7.4.13 External NTC Monitoring (TS)
      14. 7.4.14 Thermal Regulation and Protection
      15. 7.4.15 Status Outputs (CHG, PG)
      16. 7.4.16 Boost Mode Operation
        1. 7.4.16.1 PWM Controller in Boost Mode
        2. 7.4.16.2 Burst Mode during Light Load
        3. 7.4.16.3 CHG and PG During Boost Mode
        4. 7.4.16.4 Protection in Boost Mode
          1. 7.4.16.4.1 Output Over-Voltage Protection
          2. 7.4.16.4.2 Output Over-Current Protection
          3. 7.4.16.4.3 Battery Voltage Protection
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application, External Discharge FET
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Inductor and Capacitor Selection Guidelines
      2. 8.2.2 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Requirements for SYS Output
    2. 9.2 Requirements for Charging
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The following provides some guidelines:

  • Place 1µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible.
  • Connect the GND of the PMID and IN caps as close as possible.
  • Place 4.7µF input capacitor as close to IN pin and PGND pin as possible to make high frequency current loop area as small as possible.
  • The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin.
  • Place all decoupling capacitors close to their respective IC pin and as close as to PGND as possible. Do not place components such that routing interrupts power stage currents. All small control signals should be routed away from the high current paths.
  • The PCB should have a ground plane (return) connected directly to the return of all components through vias. Two vias per capacitor for power-stage capacitors and one via per capacitor for small-signal components. It is also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results.
  • The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET.
  • For high-current applications, the balls for the power paths should be connected to as much copper in the board as possible. This allows better thermal performance as the board pulls heat away from the IC.

10.2 Layout Example

It is important to pay special attention to the PCB layout. Figure 30 provides a sample layout for the high current paths of the bq24266RGE.

bq24266 qfn24_PCB_SLUSBK7.gif Figure 30. Recommended bq24266 PCB Layout for QFN Package

spacer