SLUSBD1B MARCH   2013  – September 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Pin Configuration and Function
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SMBus Timing Characteristics
    8. 5.8 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Switching Frequency Adjust
      2. 6.3.2  High Accuracy Current Sense Amplifiers
      3. 6.3.3  Charger Timeout
      4. 6.3.4  Input Over-Current Protection (ACOC)
      5. 6.3.5  Converter Over-Current Protection
      6. 6.3.6  Battery Over-Voltage Protection (BATOVP)
      7. 6.3.7  System Over-Voltage Protection (SYSOVP)
      8. 6.3.8  Thermal Shutdown Protection (TSHUT)
      9. 6.3.9  Adapter Over-Voltage Protection (ACOVP)
      10. 6.3.10 Adapter Detect and ACOK Output
      11. 6.3.11 ACFET/RBFET Control
      12. 6.3.12 DPM
      13. 6.3.13 Buck Converter Power up
    4. 6.4 Device Functional Modes
      1. 6.4.1 LDO Mode and Minimum System Voltage
      2. 6.4.2 PWM Mode Converter Operation
      3. 6.4.3 Continuous Conduction Mode (CCM)
      4. 6.4.4 Discontinuous Conduction Mode (DCM)
      5. 6.4.5 PFM Mode
      6. 6.4.6 Learn Mode
      7. 6.4.7 IDPM Disable at Battery Removal
    5. 6.5 Programming
      1. 6.5.1 SMBus Communication
        1. 6.5.1.1 SMBus Interface
          1. 6.5.1.1.1 Write-Word Format
          2. 6.5.1.1.2 Read-Word Format
        2. 6.5.1.2 SMBus Commands
        3. 6.5.1.3 Setting Charger Options
        4. 6.5.1.4 Setting the Charge Current
        5. 6.5.1.5 Setting the Max Charge Voltage
        6. 6.5.1.6 Setting the Minimum System Voltage
        7. 6.5.1.7 Setting Input Current
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Inductor Selection
        2. 7.2.2.2 Input Capacitor
        3. 7.2.2.3 Output Capacitor
        4. 7.2.2.4 Power MOSFETs Selection
        5. 7.2.2.5 Input Filter Design
      3. 7.2.3 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Function

RGR Package
20-Pin VQFN
(Top View)
bq24715 pinout_lusbd1.gif

Pin Descriptions

PIN NAME I/O DESCRIPTION
1 ACN I Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for common-mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2 ACP I Input current sense resistor positive input. Place a 1µF ceramic capacitor from ACP to GND for common-mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3 CMSRC I ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and RBFET (Q2) limits the in-rush current on CMSRC pin.
4 ACDRV O Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET (RBFET). ACDRV voltage is 6.1V above CMSRC when voltage on ACDET pin is higher than 2.4V, voltage on VCC pin is above UVLO but lower than 26V and voltage on VCC pin is 675mV above voltage on SRN pin so that ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the in-rush current on ACDRV pin.
5 ACOK O AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when voltage on ACDET pin is above 2.4V, VCC above UVLO but lower than 26V and voltage on VCC pin is 675mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up supply rail.
6 ACDET I Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK comparator and IOUT are both active.
7 IOUT O Buffered 40 times adapter or 16 times discharge current output - the differential voltage across sense resistor; selectable with SMBus command ChargeOption(). Place a 100pF or less ceramic decoupling capacitor from IOUT pin to GND.
8 SDA I/O SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ pull-up resistor according to SMBus specifications.
9 SCL I SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ pull-up resistor according to SMBus specifications.
10 CELL I Cell selection pin. For bq24715, set CELL pin Float for 2-cell, and HIGH for 3-cell. Pulling CELL to GND will provide a hardware exit function from LEARN mode, disable the input DPM function, reset the bit[5] and bit[1] in chargeoption(), and reset Maxchargevoltage() to previous CELL pin default setting value and chargecurrent() to zero. Release CELL from GND, charger will recheck CELL pin voltage and lock the new CELL pin selection.
11 BATDRV O P-channel battery FET gate driver output. This pin can go high to turn off the battery FET, go low to turn on the battery FET, or operate battery FET in linear mode to regulate the minimum system voltage when battery is depleted. Connect the source of the BATFET to the system load voltage node. Connect the drain of the BATFET to the battery pack positive node. There is an internal pull-down resistor of 50k on BATDRV to ground.
12 SRN I Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with a 0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering.
13 SRP I Charge current sense resistor positive input. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering.
14 GND I IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power pad underneath IC.
15 LODRV O Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
16 REGN O Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from REGN to GND.
17 BTST I High side power MOSFET driver power supply. Connect a 0.047µF-0.1µF capacitor from BTST to PHASE. Connect a bootstrap Schottky diode from REGN to BTST.
18 HIDRV O High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
19 PHASE I High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
20 VCC I Input supply. Use 10Ω resistor and 1µF capacitor to ground as low pass filter to limit inrush current.
PowerPAD™ I Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPad plane. Always solder PowerPad to the board, and have vias on the PowerPad plane connecting to analog ground and power ground planes. It also serves as a thermal pad to dissipate the heat.