3 Description

The CDCI6214 device is an ultra-low power clock generator. The device selects between two independent reference inputs to a phase-locked loop and generates up to four different frequencies on configurable differential output channels and also a copy of the reference clock on a LVCMOS output channel.

Each of the four output channels has a configurable integer divider. Together with the output muxes, this allows up to five different frequencies. Clock distribution dividers are reset in a deterministic way for clean clock gating and glitch-less update capability. Flexible power-down options allow to optimize the device for lowest power consumption in active and standby operation. Typically four 156.25MHz LVDS outputs consume 150mW at 1.8V. Typical RMS jitter of 386fs for 100MHz HCSL output enhances system margin for PCIe applications.

The CDCI6214 is configured using internal registers that are accessed by an I²C-compatible serial interface and internal EEPROM.

The CDCI6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM of the CDCI6214 is designed as an easy-to-use, instant-on clocking feature with low power consumption.

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽³⁾
CDCI6214	RGE (VQFN, 24)	4.00mm × 4.00mm

(1) For all available packages, see Section 13.

(2) Four LVDS outputs, 156.25MHz with crystal reference.

(3) The package size (length × width) is a nominal value and includes pins, where applicable.

Application Example CDCI6214