The CDCI6214 device is an ultra-low power clock generator. The device selects between two independent reference inputs to a phase-locked loop and generates up to four different frequencies on configurable differential output channels and also a copy of the reference clock on a LVCMOS output channel.
Each of the four output channels has a configurable integer / fractional output divider and a dedicated integer divider. Together with the output muxes, this allows up to five different frequencies. Clock distribution dividers are reset in a deterministic way for clean clock gating and glitch-less update capability. Flexible power-down options allow to optimize the device for lowest power consumption in active and standby operation. Typically four 156.25 MHz LVDS outputs consume 150 mW at 1.8V. Typical RMS jitter of 386 fs for 100 MHz HCSL output enhances system margin for PCIe applications.
The CDCI6214 is configured using internal registers that are accessed by an I2C-compatible serial interface and internal EEPROM.
The CDCI6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM make the CDCI6214 ideal as easy-to-use, instant-on clocking solution with low power consumption.
All trademarks are the property of their respective owners.
|Part number||Order||Input level||VCC out (V)||VCC core (V)||Number of outputs||Output frequency (Max) (MHz)||Output level||Operating temperature range (C)||Features||Programmability|
|-40 to 85||
||LVPECL||3.3||3.3||2||1296||LVDS||-40 to 85||3.3-V VCC/VDD||Pin configuration|