SLLS781D February   2007  – November 2014 CDCL1810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Added Thermal Information tableThermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for The SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
    4. 9.4 SDA/SCL Connections Recommendations
    5. 9.5 Device Functional Modes
    6. 9.6 Programming
      1. 9.6.1 SDA/SCL Interface
        1. 9.6.1.1 SDA/SCL Bus Slave Device Address
        2. 9.6.1.2 Command Code Definition
        3. 9.6.1.3 SDA/SCL Programming Sequence
    7. 9.7 SDA/SCL Bus Configuration Command Bitmap
      1. 9.7.1 Byte 0:
      2. 9.7.2 Byte 1:
      3. 9.7.3 Byte 2:
      4. 9.7.4 Byte 3:
      5. 9.7.5 Byte 4:
      6. 9.7.6 Byte 5:
      7. 9.7.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The CDCL1810 is a high-performance buffer that can generate 10 copies of CML clock outputs from a LVDS input. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency.

10.1.1 Clock Distribution for Multiple TI Keystone DSPs

Application_Drawing_SLLS781.pngFigure 8. CDCL1810 Application Drawing

10.1.1.1 Design Requirements

A typical application example is multi DSP chip environment. The CDCL1810 is used to buffer the common clocks to the DSP.

10.1.1.2 Detailed Design Procedure

The CDCL1810 supports output group phase alignment, if a divider gets reprogrammed. The output group phase alignment circuit will disable all outputs after changing a single divider. The outputs are enabled after the phases are aligned. See Figure 9.

If an output gets enabled/disabled, the phase synchronization circuit will ensure that all outputs are in phase. To ensure phase alignment the outputs needs to be disabled for a short time. See Figure 10.

10.1.1.3 Application Curves

output_group_divider_change_SLLS781_v2.gifFigure 9. Output Group Divider Change
individual_output_enable_disable.gifFigure 10. Individual Output Disable/Enable