SLLS781D February   2007  – November 2014 CDCL1810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Added Thermal Information tableThermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for The SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
    4. 9.4 SDA/SCL Connections Recommendations
    5. 9.5 Device Functional Modes
    6. 9.6 Programming
      1. 9.6.1 SDA/SCL Interface
        1. 9.6.1.1 SDA/SCL Bus Slave Device Address
        2. 9.6.1.2 Command Code Definition
        3. 9.6.1.3 SDA/SCL Programming Sequence
    7. 9.7 SDA/SCL Bus Configuration Command Bitmap
      1. 9.7.1 Byte 0:
      2. 9.7.2 Byte 1:
      3. 9.7.3 Byte 2:
      4. 9.7.4 Byte 3:
      5. 9.7.5 Byte 4:
      6. 9.7.6 Byte 5:
      7. 9.7.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Revision History

Changes from C Revision (September 2014) to D Revision

  • Changed the following values in AC Electrical Characteristics for Additive clock output jitter (JOUT): 188 to 180, 480 to 348, 514 to 338, 257 to 175, 500 to 347, 570 to 388, 27 to 41, 66 to 36, 72 to 42, 12 to 48, 23 to 33, 27 to 39, 3 to 0.7 Go
  • Updated Figure 8Go
  • Added Detailed Design Procedure text Go
  • Updated images for Figure 9 and Figure 10Go

Changes from B Revision (March 2011) to C Revision

  • Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
  • Added "and Automatic Output Synchronization" in FeaturesGo
  • Deleted "Clock Synthesis" and "Synthesis" from ApplicationsGo
  • Added Output Enable/Disable to Feature Description sectionGo
  • Added Figure 5 to Feature DescriptionGo

Changes from A Revision (March 2007) to B Revision

  • Changed the Decscription paragraph starting with "All device....interface".Go
  • Changed The Description of row SCL in the Pin Function table: added "SCL tolerated 1.8V on the input only." Go
  • Changed The Description of row SDA in the Pin Function table: added "SCD tolerates 1.8V on the input only." Go
  • Changed -0.3 to 4.0 to -0.3 to VDD+0.6 in ABS MAX tableGo
  • Added Thermal Information tableGo
  • Changed the VD,DOUT Test Conditions in the AC Electrical Characteristics tableGo
  • Added Note 1 to the Function Block DiagramGo
  • Added the SDA/SCL Connections Recommendations sectionGo