SLPS459A January   2014  – June 2014 CSD25310Q2

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Trademarks
    2. 6.2 Electrostatic Discharge Caution
    3. 6.3 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q2 Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Pattern
    4. 7.4 Q2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

TA = 25°C, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = –250 μA –20 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –16 V –1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –8 V –100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA –0.55 –0.85 –1.10 V
RDS(on) Drain-to-Source On Resistance VGS = –1.8 V, IDS = –5 A 59.0 89.0 mΩ
VGS = –2.5 V, IDS = –5 A 27.0 32.5 mΩ
VGS = –4.5 V, IDS = –5 A 19.9 23.9 mΩ
gfs Transconductance VDS = –16 V, IDS = –5 A 34 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance VGS = 0 V, VDS = –10 V, f = 1 MHz 504 655 pF
COSS Output Capacitance 281 365 pF
CRSS Reverse Transfer Capacitance 16.7 21.7 pF
Rg Series Gate Resistance 1.9 Ω
Qg Gate Charge Total (–4.5 V) VDS = –10 V, IDS = –5 A 3.6 4.7 nC
Qgd Gate Charge Gate to Drain 0.5 nC
Qgs Gate Charge Gate to Source 1.1 nC
Qg(th) Gate Charge at Vth 0.6 nC
QOSS Output Charge VDS = –10 V, VGS = 0 V 5.0 nC
td(on) Turn On Delay Time VDS = –10 V, VGS = –4.5 V, IDS = –5 A
RG = 2 Ω		 8 ns
tr Rise Time 15 ns
td(off) Turn Off Delay Time 15 ns
tf Fall Time 5 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = –5 A, VGS = 0 V –0.8 –1.0 V
Qrr Reverse Recovery Charge VDD = –10 V, IF = –5 A, di/dt = 200 A/μs 9.2 nC
trr Reverse Recovery Time 13 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Thermal Resistance Junction to Case(1) 4.5 °C/W
RθJA Thermal Resistance Junction to Ambient(1)(2) 55
(1) RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
m0161-01_lps202.gif
 Max RθJA = 55 when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu.
m0161-02_lps202.gif
 Max RθJA = 215 when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
graph01_SLPS459.png
Figure 1. Transient Thermal Impedance
graph02_SLPS459.png
Figure 2. Saturation Characteristics
graph04p3_SLPS459.png
Figure 4. Gate Charge
graph06_SLPS459.png
Figure 6. Threshold Voltage vs Temperature
graph08_SLPS459.png
Figure 8. Normalized On-State Resistance vs Temperature
graph10_SLPS459.png
Figure 10. Maximum Safe Operating Area
graph03_SLPS459.png
Figure 3. Transfer Characteristics
graph05_SLPS459.png
Figure 5. Capacitance
graph07_SLPS459.png
Figure 7. On-State Resistance vs Gate-to-Source Voltage
graph09_SLPS459.png
Figure 9. Typical Diode Forward Voltage
graph12_SLPS459.png
Figure 11. Maximum Drain Current vs Temperature