DLPS123C february   2019  – july 2023 DLP2010

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MINNOMMAXUNIT
LPSDR
tRRise slew rate(1)(30% to 80%) × VDD, Figure 6-313V/ns
tFFall slew rate(1)(70% to 20%) × VDD, Figure 6-313V/ns
tRRise slew rate(2)(20% to 80%) × VDD, Figure 6-30.25V/ns
tFFall slew rate(2)(80% to 20%) × VDD, Figure 6-30.25V/ns
tCCycle time LS_CLK,Figure 6-27.78.3ns
tW(H)Pulse duration LS_CLK high50% to 50% reference points, Figure 6-23.1ns
tW(L)Pulse duration LS_CLK low50% to 50% reference points, Figure 6-23.1ns
tSUSetup timeLS_WDATA valid before LS_CLK ↑, Figure 6-21.5ns
tHHold timeLS_WDATA valid after LS_CLK ↑, Figure 6-21.5ns
tWINDOWWindow time(1)(3)Setup time + Hold time, Figure 6-23.0ns
tDERATINGWindow time derating(1)(3)For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-50.35ns
SubLVDS
tRRise slew rate20% to 80% reference points, Figure 6-40.71V/ns
tFFall slew rate80% to 20% reference points, Figure 6-40.71V/ns
tCCycle time LS_CLK,Figure 6-61.611.67ns
tW(H)Pulse duration DCLK high50% to 50% reference points, Figure 6-60.71ns
tW(L)Pulse duration DCLK low50% to 50% reference points, Figure 6-60.71ns
tSUSetup timeD(0:3) valid before
DCLK ↑ or DCLK ↓, Figure 6-6
tHHold timeD(0:3) valid after
DCLK ↑ or DCLK ↓, Figure 6-6
tWINDOWWindow timeSetup time + Hold time, Figure 6-6, Figure 6-73.0ns
tLVDS-ENABLE+REFGENPower-up receiver(4)2000ns
Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.
Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
GUID-36AF8701-52D5-4159-AA57-9359388F078D-low.gif
Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
Figure 6-2 LPSDR Switching Parameters
GUID-D46E7303-BCC7-441D-87E8-AD1CF4EA195B-low.gif Figure 6-3 LPSDR Input Rise and Fall Slew Rate
GUID-1532DAD3-3512-48D3-87B5-5EAA95D44C92-low.gif Figure 6-4 SubLVDS Input Rise and Fall Slew Rate
GUID-6FD74061-9E7B-424F-99BC-3F8C818A1F22-low.gifFigure 6-5 Window Time Derating Concept
GUID-D0564217-C19A-4D8F-9333-B025A5FC59FD-low.gif Figure 6-6 SubLVDS Switching Parameters
GUID-C507B75D-E55A-44E2-81EB-623D0D644DB9-low.gif
Note: Refer to Section 7.3.3 for details.
Figure 6-7 High-Speed Training Scan Window
GUID-9F7FB879-25A3-4BDB-980F-1B985ECE90BD-low.gif Figure 6-8 SubLVDS Voltage Parameters
GUID-A9408626-5AB2-406A-825F-C18A387555F6-low.gif
VSubLVDS(max) = VCM(max) + | ½ × VID(max) |
VSubLVDS(min) = VCM(min) – | ½ × VID(max) |
Figure 6-9 SubLVDS Waveform Parameters
GUID-399A8B59-0A04-483D-8A44-07BB7D8F1B4C-low.gif Figure 6-10 SubLVDS Equivalent Input Circuit
GUID-279FE87F-484A-48AD-BAF3-43999666272D-low.gif Figure 6-11 LPSDR Input Hysteresis
GUID-BF22D053-A723-47E2-901D-77E9007C11E2-low.gif Figure 6-12 LPSDR Read Out
GUID-EF432CDC-064E-4862-9823-9BA35705CA63-low.gif
See Section 7.3.4 for more information.
Figure 6-13 Test Load Circuit for Output Propagation Measurement