SNLS505E August   2016  – March 2019 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 IO Pins State During Reset
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Power-Up Timing
    7. 7.7  Timing Requirements, Reset Timing
    8. 7.8  Timing Requirements, Serial Management Timing
    9. 7.9  Timing Requirements, 100 Mbps MII Transmit Timing
    10. 7.10 Timing Requirements, 100 Mbps MII Receive Timing
    11. 7.11 Timing Requirements, 10 Mbps MII Transmit Timing
    12. 7.12 Timing Requirements, 10 Mbps MII Receive Timing
    13. 7.13 Timing Requirements, RMII Transmit Timing
    14. 7.14 Timing Requirements, RMII Receive Timing
    15. 7.15 Timing Requirements, RGMII
    16. 7.16 Normal Link Pulse Timing
    17. 7.17 Auto-Negotiation Fast Link Pulse (FLP) Timing
    18. 7.18 10BASE-Te Jabber Timing
    19. 7.19 MII: 100BASE-TX Transmit Latency Timing
    20. 7.20 MII: 100BASE-TX Receive Latency Timing
    21. 7.21 Timing Diagrams
    22. 7.22 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Energy Efficient Ethernet
        1. 8.3.1.1 EEE Overview
        2. 8.3.1.2 EEE Negotiation
      2. 8.3.2 Wake-on-LAN Packet Detection
        1. 8.3.2.1 Magic Packet Structure
        2. 8.3.2.2 Magic Packet Example
        3. 8.3.2.3 Wake-on-LAN Configuration and Status
      3. 8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 8.3.4 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1  MAC Interfaces
        1. 8.4.1.1 Media Independent Interface (MII)
        2. 8.4.1.2 Reduced Media Independent Interface (RMII)
        3. 8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
      2. 8.4.2  Serial Management Interface
        1. 8.4.2.1 Extended Register Space Access
        2. 8.4.2.2 Write Address Operation
        3. 8.4.2.3 Read Address Operation
        4. 8.4.2.4 Write (No Post Increment) Operation
        5. 8.4.2.5 Read (No Post Increment) Operation
        6. 8.4.2.6 Write (Post Increment) Operation
        7. 8.4.2.7 Read (Post Increment) Operation
        8. 8.4.2.8 Example Write Operation (No Post Increment)
        9. 8.4.2.9 Example Read Operation (No Post Increment)
      3. 8.4.3  100BASE-TX
        1. 8.4.3.1 100BASE-TX Transmitter
          1. 8.4.3.1.1 Code-Group Encoding and Injection
          2. 8.4.3.1.2 Scrambler
          3. 8.4.3.1.3 NRZ to NRZI Encoder
          4. 8.4.3.1.4 Binary to MLT-3 Converter
        2. 8.4.3.2 100BASE-TX Receiver
      4. 8.4.4  100BASE-FX
        1. 8.4.4.1 100BASE-FX Transmit
        2. 8.4.4.2 100BASE-FX Receive
      5. 8.4.5  10BASE-Te
        1. 8.4.5.1 Squelch
        2. 8.4.5.2 Normal Link Pulse Detection and Generation
        3. 8.4.5.3 Jabber
        4. 8.4.5.4 Active Link Polarity Detection and Correction
      6. 8.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 8.4.7  Auto-MDIX Resolution
      8. 8.4.8  Loopback Modes
        1. 8.4.8.1 Near-End Loopback
        2. 8.4.8.2 MII Loopback
        3. 8.4.8.3 PCS Loopback
        4. 8.4.8.4 Digital Loopback
        5. 8.4.8.5 Analog Loopback
        6. 8.4.8.6 Far-End (Reverse) Loopback
      9. 8.4.9  BIST Configurations
      10. 8.4.10 Cable Diagnostics
        1. 8.4.10.1 TDR
      11. 8.4.11 Fast Link Down Functionality
    5. 8.5 Programming
      1. 8.5.1 Hardware Bootstrap Configurations
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Characteristics
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Characteristics

The following data was measured using a DP83822 evaluation module. All the power dissipation numbers are measured at nominal voltage under typical temperature of 25°C. Center tap must be connected to the same potential as the analog supply rail (AVD).

Table 145. Power Supply Characteristics(1)

PARAMETER TEST CONDITIONS MAGNETIC SUPPLY
(mA)
AVD SUPPLY
(mA)
VDDIO SUPPLY
(mA)
TOTAL POWER
(mW)
3.3-V AVD/CT AND 3.3-V VDDIO
100BASE-TX MII, Link-Up, No Traffic 22 36 15 241
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets, 25oC 22 36 21 261
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets, -40oC 22 25 20 221
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets, 125oC 22 52 22 317
RMII, Link-Up, No Traffic 22 36 6 211
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 7 215
RGMII, Link-Up, No Traffic 22 36 8 218
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 9 221
10BASE-Te MII, Link-Up, No Traffic 2 18 7 89
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 18 7 244
RMII, Link-Up, No Traffic 2 18 6 86
RMII, Link-Up, 960ns IPG (100% Utilization), 1514-byte Packets 49 18 6 241
RGMII, Link-Up, No Traffic 2 18 7 89
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 18 7 244
Passive Sleep RMII, bits[15:12] = 0b0111 in register 0x0011 2 16 6 79
Active Sleep RMII, bits[15:12] = 0b0110 in register 0x0011 2 16 6 79
IEEE Power Down RMII, bits[11] = 1 in register 0x0000 2 4 6 40
Deep Power Down RMII, bits[11] = 1 in register 0x0000 and bit[2] = 1 in register 0x0428 2 3 6 36
Energy Efficient Ethernet TX and RX LPI, RMII 2 17 6 83
3.3-V AVD/CT AND 1.8-V VDDIO
100BASE-TX MII, Link-Up, No Traffic 22 36 10 209
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 12 213
RMII, Link-Up, No Traffic 22 36 3 197
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 4 199
RGMII, Link-Up, No Traffic 22 36 5 200
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 5 200
10BASE-Te MII, Link-Up, No Traffic 2 18 4 73
MII, Link-Up, 960ns IPG (100% Utilization), 1514-byte Packets 49 18 4 228
RMII, Link-Up, No Traffic 2 18 3 71
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 18 3 227
RGMII, Link-Up, No Traffic 2 18 4 73
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 18 4 228
Passive Sleep RMII, bits[15:12] = 0b0111 in register 0x0011 2 16 3 65
Active Sleep RMII, bits[15:12] = 0b0110 in register 0x0011 2 16 3 65
IEEE Power Down RMII, bits[11] = 1 in register 0x0000 2 4 3 25
Deep Power Down RMII, bits[11] = 1 in register 0x0000 and bit[2] = 1 in register 0x0428 2 3 3 22
Energy Efficient Ethernet TX and RX LPI, RMII 2 17 3 68
1.8-V AVD/CT AND 3.3-V VDDIO
100BASE-TX MII, Link-Up, No Traffic 22 36 15 154
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 21 174
RMII, Link-Up, No Traffic 22 36 6 124
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 7 128
RGMII, Link-Up, No Traffic 22 36 8 131
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 9 134
10BASE-Te MII, Link-Up, No Traffic 1 17 7 56
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 17 7 142
RMII, Link-Up, No Traffic 1 17 6 52
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 17 6 139
RGMII, Link-Up, No Traffic 1 17 7 56
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 17 7 142
Passive Sleep RMII, bits[15:12] = 0b0111 in register 0x0011 1 16 6 50
Active Sleep RMII, bits[15:12] = 0b0110 in register 0x0011 1 16 6 50
IEEE Power Down RMII, bits[11] = 1 in register 0x0000 1 4 6 29
Deep Power Down RMII, bits[11] = 1 in register 0x0000 and bit[2] = 1 in register 0x0428 1 3 6 27
Energy Efficient Ethernet TX and RX LPI, RMII 1 17 6 52
1.8-V AVD/CT AND 1.8-V VDDIO
100BASE-TX MII, Link-Up, No Traffic 22 36 10 122
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 12 126
RMII, Link-Up, No Traffic 22 36 3 110
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 4 112
RGMII, Link-Up, No Traffic 22 36 5 113
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 22 36 5 113
10BASE-Te MII, Link-Up, No Traffic 1 17 4 40
MII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 17 4 126
RMII, Link-Up, No Traffic 1 17 3 38
RMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 17 3 124
RGMII, Link-Up, No Traffic 1 17 4 40
RGMII, Link-Up, 960-ns IPG (100% Utilization), 1514-byte Packets 49 17 4 126
Passive Sleep RMII, bits[15:12] = 0b0111 in register 0x0011 1 16 3 36
Active Sleep RMII, bits[15:12] = 0b0110 in register 0x0011 1 16 3 36
IEEE Power Down RMII, bits[11] = 1 in register 0x0000 1 4 3 14
Deep Power Down RMII, bits[11] = 1 in register 0x0000 and bit[2] = 1 in register 0x0428 1 3 3 13
Energy Efficient Ethernet TX and RX LPI, RMII 1 17 3 38
Ensured by production test, characterization, or design.