SNLS614C September 2018 – April 2024 DP83869HM
PRODUCTION DATA
Table 7-20 lists the memory-mapped registers for the DP83869 registers. All register offset addresses not listed in Table 7-20 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | BMCR | Basic Mode Control Register | Go |
1h | BMSR | Basic Mode Status Register | Go |
2h | PHYIDR1 | PHY Identifier Register #1 | Go |
3h | PHYIDR2 | PHY Identifier Register #2 | Go |
4h | ANAR | Auto-Negotiation Advertisement Register | Go |
5h | ALNPAR | Auto-Negotiation Link Partner Ability Register | Go |
6h | ANER | Auto-Negotiate Expansion Register | Go |
7h | ANNPTR | Auto-Negotiation Next Page Transmit Register | Go |
8h | ANLNPTR | Auto-Negotiation Link Partner Next Page Receive Register | Go |
9h | GEN_CFG1 | Configuration Register 1 | Go |
Ah | GEN_STATUS1 | Status Register 1 | Go |
Dh | REGCR | Register Control Register | Go |
Eh | ADDAR | Address or Data Register | Go |
Fh | 1KSCR | 1000BASE-T Status Register | Go |
10h | PHY_CONTROL | PHY Control Register | Go |
11h | PHY_STATUS | PHY Status Register | Go |
12h | INTERRUPT_MASK | MII Interrupt Control Register | Go |
13h | INTERRUPT_STATUS | Interrupt Status Register | Go |
14h | GEN_CFG2 | Configuration Register 2 | Go |
15h | RX_ERR_CNT | Go | |
16h | BIST_CONTROL | BIST Control Register | Go |
17h | GEN_STATUS2 | Status Register 2 | Go |
18h | LEDS_CFG1 | LED Configuration Register 1 | Go |
19h | LEDS_CFG2 | LED Configuration Register 2 | Go |
1Ah | LEDS_CFG3 | LED Configuration Register 3 | Go |
1Eh | GEN_CFG4 | Configuration Register 3 | Go |
1Fh | GEN_CTRL | Control Register | Go |
25h | ANALOG_TEST_CTRL | Testmode Channel Control Register | Go |
2Ch | GEN_CFG_ENH_AMIX | Go | |
2Dh | GEN_CFG_FLD | Go | |
2Eh | GEN_CFG_FLD_THR | Go | |
31h | GEN_CFG3 | Configuration Register 4 | Go |
32h | RGMII_CTRL | RGMII Control Register | Go |
33h | RGMII_CTRL2 | Go | |
37h | SGMII_AUTO_NEG_STATUS | SGMII Autonegotiation Status Register | Go |
39h | PRBS_TX_CHK_CTRL | Go | |
3Ah | PRBS_TX_CHK_BYTE_CNT | Go | |
43h | G_100BT_REG0 | Go | |
4Fh | SERDES_SYNC_STS | Go | |
55h | G_1000BT_PMA_STATUS | Skew FIFO Status Register | Go |
6Eh | STRAP_STS | Strap Status Register | Go |
71h | DBG_PRBS_BYTE_CNT | Go | |
72h | DBG_PRBS_ERR_CNT | Go | |
7Bh | DBG_PKT_LEN_PRBS | Go | |
7Ch | DBG_IPG_LEN | Go | |
86h | ANA_RGMII_DLL_CTRL | RGMII Delay Control Register | Go |
C6h | ANA_PLL_PROG_PI | Go | |
D6h | SGMII_TESTMODE | Go | |
E9h | DSP_HYBRID_CFG2 | Go | |
FEh | LOOPCR | Loopback Configuration Register | Go |
134h | RXF_CFG | Go | |
135h | RXF_STATUS | Go | |
136h | RXF_PMATCH_DATA1 | Go | |
137h | RXF_PMATCH_DATA2 | Go | |
138h | RXF_PMATCH_DATA3 | Go | |
139h | RXF_SCRON_PASS1 | Go | |
13Ah | RXF_SCRON_PASS2 | Go | |
13Bh | RXF_SCRON_PASS3 | Go | |
13Ch | RXF_PATTERN_1 | Go | |
13Dh | RXF_PATTERN_2 | Go | |
13Eh | RXF_PATTERN_3 | Go | |
13Fh | RXF_PATTERN_4 | Go | |
140h | RXF_PATTERN_5 | Go | |
141h | RXF_PATTERN_6 | Go | |
142h | RXF_PATTERN_7 | Go | |
143h | RXF_PATTERN_8 | Go | |
144h | RXF_PATTERN_9 | Go | |
145h | RXF_PATTERN_10 | Go | |
146h | RXF_PATTERN_11 | Go | |
147h | RXF_PATTERN_12 | Go | |
148h | RXF_PATTERN_13 | Go | |
149h | RXF_PATTERN_14 | Go | |
14Ah | RXF_PATTERN_15 | Go | |
14Bh | RXF_PATTERN_16 | Go | |
14Ch | RXF_PATTERN_17 | Go | |
14Dh | RXF_PATTERN_18 | Go | |
14Eh | RXF_PATTERN_19 | Go | |
14Fh | RXF_PATTERN_20 | Go | |
150h | RXF_PATTERN_21 | Go | |
151h | RXF_PATTERN_22 | Go | |
152h | RXF_PATTERN_23 | Go | |
153h | RXF_PATTERN_24 | Go | |
154h | RXF_PATTERN_25 | Go | |
155h | RXF_PATTERN_26 | Go | |
156h | RXF_PATTERN_27 | Go | |
157h | RXF_PATTERN_28 | Go | |
158h | RXF_PATTERN_29 | Go | |
159h | RXF_PATTERN_30 | Go | |
15Ah | RXF_PATTERN_31 | Go | |
15Bh | RXF_PATTERN_32 | Go | |
15Ch | RXF_PATTERN_BYTE_MASK_1 | Go | |
15Dh | RXF_PATTERN_BYTE_MASK_2 | Go | |
15Eh | RXF_PATTERN_BYTE_MASK_3 | Go | |
15Fh | RXF_PATTERN_BYTE_MASK_4 | Go | |
16Fh | 10M_SGMII_CFG | Go | |
170h | IO_MUX_CFG | Go | |
172h | IO_MUX_GPIO_CTRL2 | Go | |
180h | TDR_GEN_CFG1 | Go | |
181h | TDR_GEN_CFG2 | Go | |
182h | TDR_SEG_DURATION1 | Go | |
183h | TDR_SEG_DURATION2 | Go | |
184h | TDR_GEN_CFG3 | Go | |
185h | TDR_GEN_CFG4 | Go | |
190h | TDR_PEAKS_LOC_A_0_1 | Go | |
191h | TDR_PEAKS_LOC_A_2_3 | Go | |
192h | TDR_PEAKS_LOC_A_4_B_0 | Go | |
193h | TDR_PEAKS_LOC_B_1_2 | Go | |
194h | TDR_PEAKS_LOC_B_3_4 | Go | |
195h | TDR_PEAKS_LOC_C_0_1 | Go | |
196h | TDR_PEAKS_LOC_C_2_3 | Go | |
197h | TDR_PEAKS_LOC_C_4_D_0 | Go | |
198h | TDR_PEAKS_LOC_D_1_2 | Go | |
199h | TDR_PEAKS_LOC_D_3_4 | Go | |
1A4h | TDR_GEN_STATUS | Go | |
1A5h | TDR_PEAKS_SIGN_A_B | Go | |
1A6h | TDR_PEAKS_SIGN_C_D | Go | |
1A8h | DBG_PRBS_PKT_CNT_1 | Go | |
1A9h | DBG_PRBS_PKT_CNT_2 | Go | |
1DFh | OP_MODE_DECODE | Go | |
1E0h | GPIO_MUX_CTRL | Go | |
1ECh | MC_LINK_LOSS | Go | |
C00h | FX_CTRL | Fiber Control Register | Go |
C01h | FX_STS | Fiber Status Register | Go |
C02h | FX_PHYID1 | Fiber PHYID Register 1 | Go |
C03h | FX_PHYID2 | Fiber PHYID Register 2 | Go |
C04h | FX_ANADV | Fiber Autonegotiation Advertisement Register | Go |
C05h | FX_LPABL | Fiber Link Partner Ability Register | Go |
C06h | FX_ANEXP | Fiber Autonegotiation Expansion Register | Go |
C07h | FX_LOCNP | Fiber LOC Next Page Register | Go |
C08h | FX_LPNP | Fiber Link Partner Next Page Register | Go |
C10h | CFG_FX_CTRL0 | Fiber Signal Detect | Go |
C18h | FX_INT_EN | Fiber Interrupt Enable Register | Go |
C19h | FX_INT_STS | Fiber Interrupt Status Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-21 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RC | R C | Read to Clear |
RH | R H | Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
WoP | W | Write |
WtoPH | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
BMCR is shown in Table 7-22.
Return to the Summary Table.
IEEE defined register to control PHY functionality.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESET | R/W | 0h | This bit controls the MII reset function. This bit is self cleared after reset is completed.
0h = Normal Operation 1h = Reset. |
14 | MII_LOOPBACK | R/W | 0h | This bit controls the MII Loopback. When enabled, this will send data back to the MAC
0h = Disable 1h = Enable |
13 | SPEED_SEL_LSB | R/W | 0h | Speed selection bits LSB[13] and MSB[6] are used to control the data rate of the ethernet link when auto-negotiation is disabled.
0h = 10Mbps 1h = 100Mbps 2h = 1000Mbps 3h = Reserved |
12 | AUTONEG_EN | R/W | 1h | Controls autonegotiation feature
0h = Autonegotiation off 1h = Autonegotiation on |
11 | PWD_DWN | R | 0h | Controls IEEE power down feature
0h = Normal Mode 1h = IEEE power down mode |
10 | ISOLATE | R/W | 0h | Isolate MAC interface pins.
0h = Normal mode 1h = MAC Isolate mode enabled |
9 | RSTRT_AUTONEG | R/WtoPH | 0h | Restart auto-negotiation
0h = Normal mode 1h = Restart autonegotiation |
8 | DUPLEX_EN | R/W | 1h | Controls Half and Full duplex mode of the ethernet link
0h = Half Duplex mode 1h = Full Duplex mode |
7 | COL_TST | R/W | 0h | Controls Collision Signal Test
0h = Disable Collision Signal Test 1h = Enable Collision Signal Test |
6 | SPEED_SEL_MSB | R | 1h | Controls data rate of ethernet link when autonegotiation is disabled. See bit 13 description for morw information. |
5-0 | RESERVED | R | 0h | Reserved |
BMSR is shown in Table 7-23.
Return to the Summary Table.
IEEE defined register to show status of PHY
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14 | 100M_FDUP | R | 1h | 100Base-TX full duplex
0h = PHY not able to perform full duplex 100Base-X 1h = PHY able to perform full duplex 100Base-X |
13 | 100M_HDUP | R | 1h | 100Base-TX halfduplex
0h = PHY not able to perform half duplex 100Base-X 1h = PHY able to perform half duplex 100Base-X |
12 | 10M_FDUP | R | 1h | 10Base-Te full duplex
0h = PHY not able to operate at 10Mbps in full duplex 1h = PHY able to operate at 10Mbps in full duplex |
11 | 10M_HDUP | R | 1h | 10Base-Te half duplex
0h = PHY not able to operate at 10Mbps in half duplex 1h = PHY able to operate at 10Mbps in half duplex |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | EXT_STS | R | 1h | Extended status for 1000Base T abilities in register 15
1h = Extended status information in register 0x0F |
7 | RESERVED | R | 0h | Reserved |
6 | MF_PREAMBLE_SUP | R | 1h | Ability to accept management frames with preamble suppressed.
0h = PHY will not accept management frames with preamble suppressed 1h = PHY will accept management frames with preamble suppressed |
5 | AUTONEG_COMP | R | 0h | Status of Autonegotiation
0h = Auto Negotiation process not completed 1h = Auto Negotiation process completed |
4 | REMOTE_FAULT | RC | 0h | Remote fault detection
0h = No remote fault condition detected 1h = Remote fault condition detected |
3 | AUTONEG_ABL | R | 1h | Autonegotiation ability
0h = PHY is not able to perform Auto-Negotiation 1h = PHY is able to perform Auto-Negotiation |
2 | LINK_STS1 | R | 0h | Link Status This is latch low and needs to be read twice for valid link up 0h = Link down 1h = Link up |
1 | JABBER_DTCT | RC | 0h | Jabber detected
0h = No jabber detected 1h = Jabber detected |
0 | EXT_CAPBLTY | R | 1h | Extended register capabilities
0h = Basic register set capabilities 1h = Extended register set capabilities |
PHYIDR1 is shown in Table 7-24.
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The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83869. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if esired. The PHY Identifier is intended to support network management. Texas Instruments' IEEE assigned OUI is 080028h.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | OUI_MSB | R | 2000h | OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are stored in bits 15 to 0 of this register respectively. Bit numbering for OUI goes from 1 (MSB) to 24(LSB). The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). |
PHYIDR2 is shown in Table 7-25.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | OUI_LSB | R | 28h | OUI Least Significant Bits: Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of this register respectively. |
9-4 | MODEL_NUM | R | Fh | Model number: The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9). |
3-0 | REVISION_NUM | R | 1h | Revision number: Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). This field will be incremented for all major device changes. |
ANAR is shown in Table 7-26.
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This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NEXT_PAGE_1_ADV | R/W | 0h | Next Page Advertisement
0h = Do not advertise desire to send additional SW next pages 1h = Advertise desire to send additional SW next pages |
14 | RESERVED | R | 0h | Reserved |
13 | REMOTE_FAULT_ADV | R/W | 0h | Remote Fault Advertisement
0h = Do not advertise remote fault event detection 1h = Advertise remote fault event detection |
12 | ANAR_BIT12 | R/W | 0h | |
11 | ASYMMETRIC_PAUSE_ADV | R/W | 0h | 1b = Advertise asymmetric pause ability 0b = Do not advertise asymmetric pause ability |
10 | PAUSE_ADV | R/W | 0h | 0h = Do not advertise pause ability 1h = Advertise pause ability |
9 | G_100BT_4_ADV | R/W | 0h | 100BT-4 is not supported |
8 | G_100BTX_FD_ADV | R/W | 0h | 100Base-TX Full Duplex. Default depends on strap, non strap default '1'.
0h = Do not advertise 100Base-TX Full Duplex ability 1h = Advertise 100Base-TX Full Duplex ability |
7 | G_100BTX_HD_ADV | R/W | 0h | 100Base-TX Half Duplex. Default depends on strap, non strap default '1'.
0h = Do not advertise 100Base-TX Half Duplex ability 1h = Advertise 100Base-TX Half Duplex ability |
6 | G_10BT_FD_ADV | R/W | 0h | Default depends on strap, non strap default '1'
0h = Do not advertise 10Base-T Full Duplex ability 1h = Advertise 10Base-T Full Duplex ability |
5 | G_10BT_HD_ADV | R/W | 0h | Default depends on strap, non strap default '1'
0h = Do not advertise 10Base-T Half Duplex ability 1h = Advertise 10Base-T Half Duplex ability |
4-0 | SELECTOR_FIELD_ADV | R/W | 1h | Technology selector field (802.3 == 00001) |
ALNPAR is shown in Table 7-27.
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This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful Auto-Negotiation if Next pages are supported.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NEXT_PAGE_1_LP | R | 0h | 0h = Link Partner does not advertise desire to send additional SW next pages 1h = Link Partner advertises desire to send additional SW next pages |
14 | ACKNOWLEDGE_1_LP | R | 0h | 0h = Link Partner does not acknowledge reception of link partner's link code word 1h = Link Partner acknowledges reception of link partner's link code word |
13 | REMOTE_FAULT_LP | R | 0h | 0h = Link Partner does not advertise remote fault event detection 1h = Link Partner advertises remote fault event detection |
12 | RESERVED | R | 0h | Reserved |
11 | ASYMMETRIC_PAUSE_LP | R | 0h | 0h = Link Partner does not advertise asymmetric pause ability 1h = Link Partner advertises asymmetric pause ability |
10 | PAUSE_LP | R | 0h | 0h = Link Partner does not advertise pause ability 1h = Link Partner advertises pause ability |
9 | G_100BT4_LP | R | 0h | 0h = Link Partner does not advertise 100Base-T4 ability 1h = Link Partner advertises 100Base-T4 ability |
8 | G_100BTX_FD_LP | R | 0h | 0h = Link Partner does not advertise 100Base-TX Full Duplex ability 1h = Link Partner advertises 100Base-TX Full Duplex ability |
7 | G_100BTX_HD_LP | R | 0h | 0h = Link Partner does not advertise 100Base-TX Half Duplex ability 1h = Link Partner advertises 100Base-TX Half Duplex ability |
6 | G_10BT_FD_LP | R | 0h | 0h = Link Partner does not advertise 10Base-T Full Duplex ability 1h = Link Partner advertises 10Base-T Full Duplex ability |
5 | G_10BT_HD_LP | R | 0h | 0h = Link Partner does not advertise 10Base-T Half Duplex ability 1h = Link Partner advertises 10Base-T Half Duplex ability |
4-0 | SELECTOR_FIELD_LP | R | 0h | Technology selector field |
ANER is shown in Table 7-28.
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This register contains additional Local Device and Link Partner status information.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R | 0h | Reserved |
6 | RX_NEXT_PAGE_LOC_ABLE | R | 1h | 0h = Received Next Page storage location is not specified by bit 6.5 1h = Received Next Page storage location is specified by bit 6.5 |
5 | RX_NEXT_PAGE_STOR_LOC | R | 1h | 0h = Link Partner Next Pages are stored in register 5 1h = Link Partner Next Pages are stored in register 8 |
4 | PRLL_TDCT_FAULE | RC | 0h | THIS STATUS IS LH (Latched-High)
0h = A fault has not been detected during the parallel detection process 1h = A fault has been detected during the parallel detection process |
3 | LP_NP_ABLE | R | 0h | 0h = Link partner is not able to exchange next pages 1h = Link partner is able to exchange next pages |
2 | LOCAL_NP_ABLE | R | 1h | 0h = Local device is not able to exchange next pages 1h = Local device is able to exchange next pages |
1 | PAGE_RECEIVED_1 | RC | 0h | THIS STATUS IS LH (Latched-High)
0h = A new page has not been received 1h = A new page has been received |
0 | LP_AUTONEG_ABLE | R | 0h | 0h = Link partner is not Auto-Negotiation able 1h = Link partner is Auto-Negotiation able |
ANNPTR is shown in Table 7-29.
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This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NEXT_PAGE_2_ADV | R/W | 0h | 0h = Do not advertise desire to send additional next pages 1h = Advertise desire to send additional next pages |
14 | RESERVED | R | 0h | Reserved |
13 | MESSAGE_PAGE | R/W | 1h | 0h = Current page is an unformatted page 1h = Current page is a message page |
12 | ACKNOWLEDGE2 | R/W | 0h | 0h = Do not set the ACK2 bit 1h = Set the ACK2 bit |
11 | TOGGLE | R | 0h | Toggles every page. Initial value is !4.11 |
10-0 | MESSAGE_UNFORMATTED | R/W | 1h | Contents of the message/unformatted page |
ANLNPTR is shown in Table 7-30.
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This register contains the next page information sent by the Link Partner during Auto-Negotiation.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NEXT_PAGE_2_LP | R | 0h | 0h = Link partner does not advertise desire to send additional next pages 1h = Link partner advertises desire to send additional next pages |
14 | ACKNOWLEDGE_2_LP | R | 0h | 0h = Link partner does not acknowledge reception of link code work 1h = Link partner acknowledges reception of link code word |
13 | MESSAGE_PAGE_LP | R | 1h | 0h = Received page is an unformatted page 1h = Received page is a message page |
12 | ACKNOWLEDGE2_LP | R | 0h | 0h = Link partner does not set the ACK2 bit 1h = Link partner sets the ACK2 bit |
11 | TOGGLE_LP | R | 0h | Toggles every page. Initial value is !5.11 |
10-0 | MESSAGE_UNFORMATTED_LP | R | 1h | Contents of the message/unformatted page |
GEN_CFG1 is shown in Table 7-31.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | TEST_MODE | R/W | 0h | 0h = Normal Mode 1h = Test Mode 1 - Transmit Waveform Test 2h = Test Mode 2 - Transmit Jitter Test (Master Mode) 3h = Test Mode 3 - Transmit Jitter Test (Slave Mode) 4h = Test Mode 4 - Transmit Distortion Test 5h = Test Mode 5 - Scrambled MLT3 Idles 6h = Test Mode 6 - Repetitive 0001 sequence 7h = Test Mode 7 - Repetitive {Pulse, 63 zeros} |
12 | MASTER_SLAVE_MAN_CFG_EN | R/W | 0h | 1b = Enable manual Master/Slave configuration 0b = Do not enable manual Master/Slave configuration |
11 | MASTER_SLAVE_MAN_CFG_VAL | R/W | 0h | 1b = Manual configure as Master 0b = Manual configure as Slave |
10 | PORT_TYPE | R/W | 0h | 1b = Multi-port device 0b = Single-port device |
9 | G_1000BT_FD_ADV | R/W | 1h | Default depends on strap
0h = Do not advertise 1000Base-T Full Duplex ability 1h = Advertise 1000Base-T Full Duplex ability |
8 | G_1000BT_HD_ADV | R/W | 1h | Default depends on strap
0h = Do not advertise 1000Base-T Half Duplex ability 1h = Advertise 1000Base-T Half Duplex ability |
7 | TDR_AUTO_RUN | R/W | 0h | TDR Auto Run at link down:
0h = Disable automatic execution of TDR 1h = Enable execution of TDR procedure after link down event |
6-0 | RESERVED | R | 0h | Reserved |
GEN_STATUS1 is shown in Table 7-32.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | MS_CONFIG_FAULT | RC | 0h | 1 = Master/Slave configuration fault detected 0 = No Master/Slave configuration fault detected THIS STATUS IS LH (Latched-High) |
14 | MS_CONFIG_RES | R | 0h | 1 = Local PHY configuration resolved to Master 0 = Local PHY configuration resolved to Slave |
13 | LOC_RCVR_STATUS_1 | R | 0h | 1 = Local receiver is OK 0 = Local receiver is not OK |
12 | REM_RCVR_STATUS | R | 0h | 1 = Remote receiver is OK 0 = Remote receiver is not OK |
11 | LP_1000BT_FD_ABILITY | R | 0h | 1 = Link partner supports 1000Base-T Full Duplex ability 0 = Link partner does not support 1000Base-T Full Duplex ability |
10 | LP_1000BT_HD_ABILITY | R | 0h | 1 = Link partner supports 1000Base-T Half Duplex ability 0 = Link partner does not support 1000Base-T Half Duplex ability |
9-8 | RESERVED | R | 0h | Reserved |
7-0 | IDLE_ERR_COUNT | R | 0h | 1000Base-T Idle Error Counter |
REGCR is shown in Table 7-33.
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This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR also contains selection bits for auto increment of the data register. This register contains the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCR also contains selection bits (15:14) for the address auto-increment mode of ADDAR.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | G_FUNCTION | R/W | 0h | 00 = Address 01 = Data, no post increment 10 = Data, post increment on read and write 11 = Data, post increment on write only |
13-5 | RESERVED | R | 0h | Reserved |
4-0 | DEVAD | R/W | 0h | Device Address |
ADDAR is shown in Table 7-34.
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This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D) to provide the access by indirect read/write mechanism to the extended register set.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | ADDR_DATA | R/W | 0h | If register 13.15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data register |
1KSCR is shown in Table 7-35.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | G_1000BX_FD | R | 1h | 1 = PHY supports 1000Base-X Full Duplex capability 0 = PHY does not support 1000Base-X Full Duplex capability |
14 | G_1000BX_HD | R | 1h | 1 = PHY supports 1000Base-X Half Duplex capability 0 = PHY does not support 1000Base-X Half Duplex capability |
13 | G_1000BT_FD | R | 1h | 1 = PHY supports 1000Base-T Full Duplex capability 0 = PHY does not support 1000Base-T Full Duplex capability |
12 | G_1000BT_HD | R | 1h | 1 = PHY supports 1000Base-T Half Duplex capability 0 = PHY does not support 1000Base-T Half Duplex capability |
11-0 | RESERVED | R | 0h | Reserved |
PHY_CONTROL is shown in Table 7-36.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | TX_FIFO_DEPTH | R/W | 1h | FIFO is enabled only in the following modes:
1000BaseT + GMII, 10BaseT/100BaseTX/1000BaseT + SGMII
0h = 3 bytes/nibbles (1000Mbps/Other Speeds) 1h = 4 bytes/nibbles (1000Mbps/Other Speeds) 2h = 6 bytes/nibbles (1000Mbps/Other Speeds) 3h = 8 bytes/nibbles (1000Mbps/Other Speeds) |
13-12 | RX_FIFO_DEPTH | R/W | 1h | FIFO is enabled only when SGMII is used
0h = 3 bytes/nibbles (1000Mbps/Other Speeds) 1h = 4 bytes/nibbles (1000Mbps/Other Speeds) 2h = 6 bytes/nibbles (1000Mbps/Other Speeds) 3h = 8 bytes/nibbles (1000Mbps/Other Speeds) |
11 | RESERVED | R/W | 0h | Reserved |
10 | FORCE_LINK_GOOD | R/W | 0h | 0h = Do Normal operation 1h = Force Link OK if speed is 1G |
9-8 | POWER_SAVE_MODE | R/W | 0h | 0h = Normal mode 1h = Reserved 2h = Active Sleep mode 3h = Passive Sleep mode |
7 | RESERVED | R/W | 0h | Reserved |
6-5 | MDI_CROSSOVER_MODE | R/W | 2h | Default depends on strap
0h = Manual MDI configuration 1h = Manual MDI-X configuration Ah = Enable automatic crossover Bh = Enable automatic crossover |
4 | DISABLE_CLK_125 | R/W | 0h | 0h = Enable CLK125 1h = Disable CLK125 |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LINE_DRIVER_INV_EN | R/W | 0h | This bit is not applicable in Mirror mode
0h = Do not Invert LD transmission 1h = Invert LD transmission |
0 | DISABLE_JABBER | R/W | 0h | 0h = Enable Jabber function 1h = Disable Jabber function |
PHY_STATUS is shown in Table 7-37.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | SPEED_SEL | R | 0h | 00 = 10Mbps 01 = 100Mbps 10 = 1000Mbps 11 = Reserved |
13 | DUPLEX_MODE_ENV | R | 0h | 1 = Full duplex 0 = Half duplex |
12 | PAGE_RECEIVED_2 | RC | 0h | 1 = Page received 0 = Page not received THIS BIT IS LH (Latched-High), meaning that if this bit detects "Page received," it will hold the value '1' until the register is read. The second read will be '0' if there have been no further "Page received." |
11 | SPEED_DUPLEX_RESOLVED | R | 0h | 1 = Auto-Negotiation completed or disabled 0 = Auto-Negotiation enabled and not completed |
10 | LINK_STATUS_2 | R | 0h | 1 = Link is up 0 = Link is down |
9 | MDI_X_MODE_CD_1 | R | 0h | 1 = MDI-X 0 = MDI |
8 | MDI_X_MODE_AB_1 | R | 0h | 1 = MDI-X 0 = MDI |
7 | SPEED_OPT_STATUS | R | 0h | 1 = Auto-Negotiation is currently being performed with Speed Optimization masking 1000BaseT abilities (Valid only during Auto-Negotiation) 0 = Auto-Negotiation is currently being performed without Speed Optimization |
6 | SLEEP_MODE | R | 0h | 1 = Sleep 0 = Active |
5-2 | WIRE_CROSS | R | 0h | Indicates channels [D,C,B,A] polarity in 1000BT link 1 = Channel polarity is reversed 0 = Channel polarity is normal |
1 | DATA_POLARITY | R | 0h | 1 = 10BT is in normal polarity 0 = 10BT is in reversed polarity |
0 | JABBER_DTCT_2 | R | 0h | 1 = Jabber 0 = No Jabber |
INTERRUPT_MASK is shown in Table 7-38.
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This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be enabled by setting bits in the MII Interrupt Control Register (MICR). If the corresponding enable bit in the register is set, an interrupt is generated if the event occurs.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | AUTONEG_ERR_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
14 | SPEED_CHNG_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
13 | DUPLEX_MODE_CHNG_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
12 | PAGE_RECEIVED_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
11 | AUTONEG_COMP_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
10 | LINK_STATUS_CHNG_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
9 | EEE_ERR_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
8 | FALSE_CARRIER_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
7 | ADC_FIFO_OVF_UNF_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
6 | MDI_CROSSOVER_CHNG_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
5 | SPEED_OPT_EVENT_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
4 | SLEEP_MODE_CHNG_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
3 | WOL_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
2 | XGMII_ERR_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
1 | POLARITY_CHNG_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
0 | JABBER_INT_EN | R/W | 0h | 1 = Enable interrupt 0 = Disable interrupt |
INTERRUPT_STATUS is shown in Table 7-39.
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This register contains event status for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. The status indications in this register will be set even if the interrupt is not enabled.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | AUTONEG_ERR | RC | 0h | 1 = Auto-Negotiation error has occurred 0 = Auto-Negotiation error has not occurred THIS BIT IS LH (Latched-High) |
14 | SPEED_CHNG | RC | 0h | 1 = Link speed has changed 0 = Link speed has not changed THIS BIT IS LH (Latched-High) |
13 | DUPLEX_MODE_CHNG | RC | 0h | 1 = Duplex mode has changed 0 = Duplex mode has not changed THIS BIT IS LH (Latched-High) |
12 | PAGE_RECEIVED | RC | 0h | 1 = Page has been received 0 = Page has not been received THIS BIT IS LH (Latched-High) |
11 | AUTONEG_COMP | RC | 0h | 1 = Auto-Negotiation has completed 0 = Auto-Negotiation has not completed THIS BIT IS LH (Latched-High) |
10 | LINK_STATUS_CHNG | RC | 0h | 1 = Link status has changed 0 = Link status has not changed THIS BIT IS LH (Latched-High) |
9 | EEE_ERR_STATUS | R | 0h | 1 = EEE error has been detected |
8 | FALSE_CARRIER | RC | 0h | 1 = Enable interrupt 0 = Disable interrupt THIS BIT IS LH (Latched-High) |
7 | ADC_FIFO_OVF_UNF | RC | 0h | 1 = Overflow / underflow has been detected in one of ADC's FIFOs THIS BIT IS LH (Latched-High) |
6 | MDI_CROSSOVER_CHNG | RC | 0h | 1 = MDI crossover has changed 0 = MDI crossover has not changed THIS BIT IS LH (Latched-High) |
5 | SPEED_OPT_EVENT | RC | 0h | 1 = MDI crossover has changed 0 = MDI crossover has not changed THIS BIT IS LH (Latched-High) |
4 | SLEEP_MODE_CHNG | RC | 0h | 1 = Sleep mode has changed 0 = Sleep mode has not changed THIS BIT IS LH (Latched-High) |
3 | WOL_STATUS | R | 0h | 1 = WoL (or pattern) packet has been received |
2 | XGMII_ERR_STATUS | R | 0h | 1 = Overflow / underflow has been detected in one of GMII / RGMII / SGMII buffers 0 = Overflow / underflow has not been detected |
1 | POLARITY_CHNG | R | 0h | 1 = Data polarity has changed 0 = Data polarity has not changed THIS BIT IS LH (Latchde-High) |
0 | JABBER | RC | 0h | 1 = Jabber detected 0 = Jabber not detected THIS BIT IS LH (Latched-High) |
GEN_CFG2 is shown in Table 7-40.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PD_DETECT_EN | R/WtoPH | 0h | 0h = Disable PD detection 1h = Enable PD (Powered Device) detection |
14 | SGMII_TX_ERR_DIS | R/W | 0h | 0h = Enable SGMII TX Error indication 1h = Disable SGMII TX Error indication |
13 | INTERRUPT_POLARITY | R/W | 1h | 0h = Interrupt pin is active high 1h = Interrupt pin is active low |
12 | SGMII_SOFT_RESET | R/WtoPH | 0h | Setting this bit will generate a soft reset pulse of SGMII. This register is WSC (write-self-clear). |
11-10 | SPEED_OPT_ATTEMPT_CNT | R/W | 2h | Selects the number of 1G link establishment attempt
failures prior to performing Speed Optimization:
0h = 1 attempt 1h = 2 attempts 2h = 4 attempts 3h = 8 attempts |
9 | SPEED_OPT_EN | R/W | 0h | 0h = Disable Speed Optimization 1h = Enable Speed Optimization |
8 | SPEED_OPT_ENHANCED_EN | R/W | 1h | In enhanced mode, speed is optimized if energy is not detected in channels C and D
0h = Disable Speed Optimization enhanced mode 1h = Enable Speed Optimization enhanced mode |
7 | SGMII_AUTONEG_EN | R/W | 1h | 0h = Disable SGMII Auto-Negotiation 1h = Enable SGMII Auto-Negotaition |
6 | SPEED_OPT_10M_EN | R/W | 1h | 0h = Disable speed optimization to 10M 1h = Enable speed optimization to 10M (If link establishments of 1G and 100M fail) |
5-4 | MII_CLK_CFG | R/W | 0h | Selects frequency of GMII_TX_CLK in 1G mode:
0h = 2.5Mhz 1h = 25Mhz 2h = Disabled 3h = Disabled |
3 | COL_FD_EN | R/W | 0h | 0h = Disable COL indication in full duplex mode 1h = Enable COL indication in full duplex mode |
2 | LEGACY_CODING_TXMODE_EN | R/W | 1h | 0h = Disable automatic selection of Legacy scrambler mode in 1G, Master mode 1h = Enable automatic selection of Legacy scrambler mode in 1G, Master mode |
1 | MASTER_SEMI_CROSS_EN | R/W | 1h | 0h = Disable semi-cross mode in 1G Master mode 1h = Enable semi-cross mode in 1G Master mode |
0 | SLAVE_SEMI_CROSS_EN | R/W | 1h | 0h = Disable semi-cross mode in 1G Slave mode 1h = Enable semi-cross mode in 1G Slave mode |
RX_ERR_CNT is shown in Table 7-41.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RX_ERROR_COUNT | R/W1C | 0h | Receive Error Counter |
BIST_CONTROL is shown in Table 7-42.
Return to the Summary Table.
This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | PACKET_GEN_EN_3:0 | R/W | 0h | These bits along controls PRBS generator.Other values are not applicable.
0h = Disable PRBS Fh = Enable Continuous PRBS |
11-10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | REV_LOOP_RX_DATA_CTRL | R/W | 0h | Reverse Loopback Receive Data Control:
This bit may only be set in Reverse Loopback mode
0h = Suppress RX packets to MAC in reverse loop 1h = Send RX packets to MAC in reverse loop |
6 | MII_LOOP_TX_DATA_CTRL | R/W | 0h | MII Loopback Transmit Data Control:
This bit may only be set in MII Loopback mode
0h = Suppress data to MDI in MII loop 1h = Transmit data to MDI in MII loop |
5-2 | LOOP_TX_DATA_MIX | R/W | 0h | Loopback Mode Select:
PCS loopback must be disabled (Bits[1:0] = 00)
0h = No Loopback 1h = Digital Loopback 2h = Analog Loopback 4h = External Loopback 8h = Reverse Loopback |
1-0 | LOOPBACK_MODE | R/W | 0h | PCS loopback select –
When configured in 1000Base-T,
X1b : Loop before 1000Base-T signal processing
When configured in 100Base-TX,
0h = See bits [5:2] 01b = Loop before scrambler 10b = Loop after scrambler, before MLT3 encoder 11b = Loop after MLT3 encoder (full TX/RX path) |
GEN_STATUS2 is shown in Table 7-43.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PD_PASS | RC | 0h | 1b = PD (Powered Device) has been successfully detected 0b = PD has not been detected |
14 | PD_PULSE_DET_ZERO | RC | 0h | 1b = PD detection mechanism has received no signal 0b = PD detection mechanism has received signal |
13 | PD_FAIL_WD | RC | 0h | 1b = PD detection mechanism watchdog has expired 0b = PD detection mechanism watchdog has not expired |
12 | PD_FAIL_NON_PD | RC | 0h | 1b = PD detection mechanism has detected a non-powered device 0b = PD detection mechanism has not detected a non-powered device |
11 | PRBS_LOCK | R | 0h | 1b = PRBS checker is locked sync) on received byte stream 0b = PRBS checker is not locked |
10 | PRBS_SYNC_LOSS | R | 0h | 1b = PRBS checker has lost sync 0b = PRBS checker has not lost sync LH - clear on read register |
9 | PKT_GEN_BUSY | R | 0h | 1b = Packet generator is in process 0b = Packet generator is not in process |
8 | SCR_MODE_MASTER_1G | R | 0h | 1b = 1G PCS (master) is in legacy encoding mode 0b = 1G PCS (master) is in normal encoding mode |
7 | SCR_MODE_SLAVE_1G | R | 0h | 1b = 1G PCS (slave) is in legacy encoding mode 0b = 1G PCS (slave) is in normal encoding mode |
6 | CORE_PWR_MODE | R | 1h | 1b = Core is in normal power mode 0b = Core is powered down or in sleep mode |
5-0 | RESERVED | R | 0h | Reserved |
LEDS_CFG1 is shown in Table 7-44.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | LED_GPIO_SEL | R/W | 6h | Source of GPIO LED, same as bits 3:0 |
11-8 | LED_2_SEL | R/W | X | See Strap Configuration section for defaults. Source of LED_2 (LED 2) , same as bits 3:0 |
7-4 | LED_1_SEL | R/W | X | See Strap Configuration section for defaults. Source of LED_1 (LED 1) , same as bits 3:0 |
3-0 | LED_0_SEL | R/W | X | See Strap Configuration section for defaults. Source of LED_0 (LED 0)
0h = link OK 1h = RX/TX activity 2h = TX activity 3h = RX activity 4h = collision detected 5h = 1000BT link is up 6h = 100 BTX link is up 7h = 10BT link is up 8h = 10/100BT link is up 9h = 100/1000BT link is up Ah = full duplex Bh = link OK (copper only) + blink on TX/RX activity Ch = NA Dh = RX_ER or TX_ER Eh = RX_ER |
LEDS_CFG2 is shown in Table 7-45.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14 | LED_GPIO_POLARITY | R/W | 1h | GPIO LED polarity:
Default depends on strap, non strap default Active High
0h = Active low 1h = Active high |
13 | LED_GPIO_DRV_VAL | R/W | 0h | If bit #12 is set, this is the value of GPIO LED |
12 | LED_GPIO_DRV_EN | R/W | 0h | Force value to LED_GPIO as per bit #13
0h = LED_GPIO is in normal operation mode 1h = Force the value of LED_GPIO |
11 | RESERVED | R | 0h | Reserved |
10 | LED_2_POLARITY | R/W | 1h | LED_2 polarity.
Default depends on strap, non strap default Active High
0h = Active low 1h = Active high |
9 | LED_2_DRV_VAL | R/W | 0h | If bit #8 is set, this is the value of LED_2 |
8 | LED_2_DRV_EN | R/W | 0h | Force value to LED_GPIO as per bit #9
0h = LED_2 is in normal operation mode 1h = Drive the value of LED_2 |
7 | RESERVED | R | 0h | Reserved |
6 | LED_1_POLARITY | R/W | 1h | LED_1 polarity:
Default depends on strap, non strap default Active High
0h = Active low 1h = Active high |
5 | LED_1_DRV_VAL | R/W | 0h | If bit #4 is set, this is the value of LED_1 |
4 | LED_1_DRV_EN | R/W | 0h | Force value to LED_GPIO as per bit #5
0h = LED_1 is in normal operation mode 1h = Drive the value of LED_1 |
3 | RESERVED | R | 0h | Reserved |
2 | LED_0_POLARITY | R/W | 1h | LED_0 polarity:
Default depends on strap, non strap default Active High
0h = Active low 1h = Active high |
1 | LED_0_DRV_VAL | R/W | 0h | If bit #1 is set, this is the value of LED_0 |
0 | LED_0_DRV_EN | R/W | 0h | Force value to LED_GPIO as per bit #1
0h = LED_0 is in normal operation mode 1h = Drive the value of LED_0 |
LEDS_CFG3 is shown in Table 7-46.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | LEDS_BYPASS_STRETCHING | R/W | 0h | 0b = Noraml Operation 1b = Bypass LEDs stretching |
1-0 | LEDS_BLINK_RATE | R/W | 2h | 00b = 20Hz (50mSec) 01b = 10Hz (100mSec) 10b = 5Hz (200mSec) 11b = 2Hz (500mSec) |
GEN_CFG4 is shown in Table 7-47.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0h | Reserved |
14 | CFG_FAST_ANEG_EN | R/W | 0h | Enable Fast ANEG mode |
13-12 | CFG_FAST_ANEG_SEL_VAL | R/W | 0h | when Fast ANEG mode enabled, value will select short timer duration 0x0 will be the shortest timers config and 0x2 the longest |
11 | CFG_ANEG_ADV_FD_EN | R/W | 0h | this but enables to declare FD also in parallel detect link, the IEEE defien on parallel detect to always declare HD, this bit allows also to declare FD in this scenario |
10 | RESTART_STATUS_BITS_EN | R/W | 0h | reset enable 1b = clear all the phy status bits (part of register 0x11) 0b = do not clear the status bit |
9 | CFG_ROBUST_AMDIX_EN | R/W | 0h | Enable Robust Auto MDI/MDIX resolution |
8 | CFG_FAST_AMDIX_EN | R/W | 0h | Enabe Fast Auto MDI-X mode |
7 | INT_OE | R/W | 0h | Interrupt Output Enable: 1b = INTN/PWDNN Pad is an Interrupt Output 0b = INTN/PWDNN Pad in an Power Down Input |
6 | FORCE_INTERRUPT | R/W | 0h | 1b = Assert interrupt pin 0b = Normal interrupt mode |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | FORCE_1G_AUTONEG_EN | R/W | 0h | 1b = Invoke Auto-Negotiation with only 1G advertised when manual speed in register 0x0000 is 1G 0b = Do not invoke Auto-Negotiation when manual speed in register 0x0000 is 1G |
2 | TDR_FAIL | R | 0h | |
1 | TDR_DONE | R | 1h | |
0 | TDR_START | R/WtoPH | 0h | 1b = Start TDR 0b = TDR Completed |
GEN_CTRL is shown in Table 7-48.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SW_RESET | R/WtoPH | 0h | Software Reset
This will reset the PHY and return registers to their default values. Registers controlled via strap pins will return back to their last strapped values.
0h = Normal mode 1h = Reset PHY |
14 | SW_RESTART | R/WtoPH | 0h | Soft Restart
Restarts the PHY without affecting registers.
0h = Normal Operation 1h = Software Reset |
13 | RESERVED | R/W | 0h | Reserved |
12-7 | RESERVED | R/W | 0h | Reserved |
6-0 | RESERVED | R/W | 0h | Reserved |
ANALOG_TEST_CTRL is shown in Table 7-49.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-10 | TM7_PULSE_SEL | R/W | 1h | Selects pulse amplitude and polarity for Test Mode 7 (See register 0x9): 00b = +2 01b = -2 10b = +1 11b = -1 |
9 | EXTND_TM7_100BT_MSB | R/W | 0h | MSB of configurable length for 100BT extended TM7 For 100BT Test Mode: repetitive sequence of "1" with configurable number of "0". Bits { 9,[3:0] } define the number of "0" to follow the "1", from 1 to 31. 0,0001 - 1,1111 : single "0" to 31 zeros. 0,0000 - clear the shiftreg. |
8 | EXTND_TM7_100BT_EN | R/W | 0h | Enable extended TM7 for 100M. NOTE1: bit 4 must be "0" for 100BT TestMode. NOTE2: 100BT testmode must be Clear before appling new Value. e.g, one need to write 0x0 before configuring new value. NOTE3: use FORCE100 for 100BT testing, via Reg0x0. |
7-5 | STIM_CH_SEL | R/W | 4h | Selects the channel(s) that outputs the test mode: If bit #7 is set, test mode is driven to all channels. If bit #7 is cleared, test mode is driven according to bits 6:5 - 00b = Channel A 01b = Channel B 10b = Channel C 11b = Channel D |
4-0 | ANALOG_TEST | R/W | 0h | Bit [4] enables 10BaseT test modes. Bits [3:0] select the 10BaseT test pattern, as follows: To operate extended TM7 for 100BT, bits 3:0 shall be configured as well - more details in bit #9 0000b = Single NLP 0001b = Single Pulse 1 0010b = Single Pulse 0 0011b = Repetitive 1 0100b = Repetitive 0 0101b = Preamble (repetitive "10") 0110b = Single 1 followed by TP_IDLE 0111b = Single 0 followed by TP_IDLE 1000b = Repetitive "1001" sequence 1001b = Random 10Base-T data 1010b = TP_IDLE_00 1011b = TP_IDLE_01 1100b = TP_IDLE_10 1101b = TP_IDLE_11 0110b = Proprietary T.M for amplitude, RFT, DCD and template for FT on tester (1000) ---> need to write register 0 0x2000 |
GEN_CFG_ENH_AMIX is shown in Table 7-50.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13-9 | CFG_FLD_WINDW_CNT | R/W | Ah | counter to define the wondow in which we lok for fast link down criteria, default 10usec |
8-4 | CFG_FAST_AMDIX_VAL | R/W | 1h | timer of the mdi/x switch cuonterin force 100m fast amdix mode, very fast as it need only to allow far end to detect energy ~4ms in default |
3-0 | CFG_ROBUST_AMDIX_VAL | R/W | Fh | the value of the timer that switch mdi/x in robust mode, this shoul be long timer to allow far end to still do parallel detect witht he IEEE ANEG timers... default ~0.5s |
GEN_CFG_FLD is shown in Table 7-51.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | CFG_FORCE_DROP_LINK_EN | R/W | 0h | Drop link (stop transmitting) when no signal is received |
14 | FLD_BYPASS_MAX_WAIT_TIMER | R/W | 0h | If set, MAX_WAIT_TIMER is skipped (and therefore link is dropped faster) |
13 | SLICER_OUT_STUCK | R | 0h | indicate slicer)out_stuck status |
12-8 | FLD_STATUS | R | 0h | Fast link down status LH - clear on read register |
7-5 | RESERVED | R | 0h | Reserved |
4-0 | CFG_FAST_LINK_DOWN_MODES | R/W | 0h | 5 bits for different fast link down option (can all work simultaniously): bit [0] - energy lost bit [1] - mse bit [2] - mlt3 errors bit [3] - rx_err bit [4] - descrambler sync loss |
GEN_CFG_FLD_THR is shown in Table 7-52.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10-8 | ENERGY_WINDOW_LEN_FLD | R/W | 2h | window length in FLD energy lost mode for energy detection accumulator |
7 | RESERVED | R | 0h | Reserved |
6-4 | ENERGY_ON_FLD_THR | R/W | 2h | energy lost threshold for FLD energy lost mode. energy_detected indication will be asserted when energy detector accumulator exceeds this threshold. |
3 | RESERVED | R | 0h | Reserved |
2-0 | ENERGY_LOST_FLD_THR | R/W | 1h | energy lost threshold for FLD energy lost mode energy_lost indication will be asserted if energy detector accumulator falls below this threshold. |
GEN_CFG3 is shown in Table 7-53.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11-9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6-5 | SGMII_AUTONEG_TIMER | R/W | 1h | Selects duration of SGMII Auto-Negotiation timer: 00: 1.6ms 01: 2µs 10: 800µs 11: 11ms |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | PORT_MIRRORING_MODE | R/W | 0h | Port mirroring mode: 0 - Disabled 1 - Enabled |
RGMII_CTRL is shown in Table 7-54.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6-5 | RGMII_RX_HALF_FULL_THR | R/W | 2h | RGMII RX sync FIFO Half-full Threshold Bits 1:0 of the 3-bit threshold field. Bit2 can be found in Reg 0x33[1]. The default setting 2 will start a FIFO read when the difference between the write and read pointer is 4. The TX/RX FIFOs have a depth of 8. Increasing the threshold from 2 to 3 will increase the latency by 1 read cycle; while decreasing the threshold from 2 to 1 will decrease latency by 1 read cycle. If the difference between ppm of the read and write clocks is significant, a half-full threshold can cause either FIFO underflow or overflow. |
4-3 | RGMII_TX_HALF_FULL_THR | R/W | 2h | RGMII TX sync FIFO Half-full Thresholds Bits 1:0 of the 3-bit threshold field. Bit2 can be found in Reg 0x33[0] See RGMII_RX_HALF_FULL_THR for more details. |
2 | SUPPRESS_TX_ERR_EN | R/W | 0h | |
1 | RGMII_TX_CLK_DELAY | R/W | 0h | RGMII Transmit Clock Delay
0h = RGMII transmit clock is shifted with respect to transmit data. 1h = RGMII transmit clock is aligned with respect to transmit data. |
0 | RGMII_RX_CLK_DELAY | R/W | 0h | RGMII Receive Clock Delay
0h = RGMII receive clock is shifted with respect to receive data. 1h = RGMII transmit clock is aligned with respect to receive data. |
RGMII_CTRL2 is shown in Table 7-55.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4 | RGMII_AF_BYPASS_EN | R/W | 0h | RGMII Async FIFO Bypass Enable: 1 = Enable RGMII Async FIFO Bypass. 0 = Normal operation. |
3 | RGMII_AF_BYPASS_DLY_EN | R/W | 0h | RGMII Async FIFO Bypass Delay Enable: 1 = Delay RX_CLK when operating in 10/100 with RGMII. 0 = Normal operation |
2 | LOW_LATENCY_10_100_EN | R/W | 0h | Low Latency 10/100 Enable: 1 = Enable low latency in 10/100 operation. 0 = Normal operation. |
1 | RGMII_RX_HALF_FULL_THR_MSB | R/W | 0h | RGMII RX sync FIFO Half-full Threshold Bit2 of the 3-bit threshold field. Bits 1:0 can be found in Reg 0x32[6:5], respectively. |
0 | RGMII_TX_HALF_FULL_THR_MSB | R/W | 0h | RGMII TX sync FIFO Half-full Threshold Bit2 of the 3-bit threshold field. Bits 1:0 can be found in Reg 0x32[4:3], respectively. |
SGMII_AUTO_NEG_STATUS is shown in Table 7-56.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R | 0h | Reserved |
1 | SGMII_PAGE_RX | R | 0h | 1b = indicate that a new auto-neg page was received |
0 | SGMII_AUTONEG_COMPLETE | R | 0h | 1b = Auto-Negotiation process completed 0b = Auto-Negotiation process not completed |
PRBS_TX_CHK_CTRL is shown in Table 7-57.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14-7 | PRBS_TX_CHK_ERR_CNT | R | 0h | Holds number of errored bytes that received by the PRBS TX checker. When TX PRBS Count Mode (see bit [1]) set to 0, count stops on 0xFF. Notes: Writing bit 7 generates a lock signal for the PRBS TX counters. Writing bit 8 generates a lock and clear signal for the PRBS TX counters |
6 | RESERVED | R | 0h | Reserved |
5 | PRBS_TX_CHK_SYNC_LOSS | R | 0h | 1b = PRBS TX checker has lost sync 0b = PRBS TX checker has not lost sync This bit is LH |
4 | PRBS_TX_CHK_LOCK_STS | R | 0h | 1b = PRBS TX checker is locked on received byte stream 0b = PRBS TX checker is not locked |
3 | RESERVED | R | 0h | Reserved |
2 | PRBS_TX_CHK_BYTE_CNT_OVF | R | 0h | If set, bytes counter reached overflow |
1 | PRBS_TX_CHK_CNT_MODE | R/W | 0h | PRBS Checker Mode 1b = Continuous mode 0b = Single Mode. |
0 | PRBS_TX_CHK_EN | R/W | 0h | If set, PRBS TX checker is enabled (PRBS TX checker is used in external reverse loop) |
PRBS_TX_CHK_BYTE_CNT is shown in Table 7-58.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PRBS_TX_CHK_BYTE_CNT | R | 0h | Holds number of total bytes that received by the PRBS TX checker. Value in this register is locked when write is done to register PRBS_TX_CHK_CTRL bit[7]or bit[8]. When PRBS Count Mode set to zero, count stops on 0xFFFF (see register 0x0016) |
G_100BT_REG0 is shown in Table 7-59.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10-7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | FAST_RX_DV | R/W | 0h | Enable Fast RX_DV for low latency in 100Mbps mode.
0h = Fast rx dv disable 1h = Fast rx dv enable |
SERDES_SYNC_STS is shown in Table 7-60.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | SYNC_STATUS | R | 0h | Synchronization Status
0h = No Sync 1h = Sync Established |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | RESERVED | R | 0h | Reserved |
G_1000BT_PMA_STATUS is shown in Table 7-61.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7-4 | PMA_MASTER_FIFO_CTRL | R | 0h | 1000Mb SFD Variation in Master Mode |
3-0 | PMA_SLAVE_FIFO_CTRL | R | 0h | 1000Mb SFD Variation in Slave Mode |
STRAP_STS is shown in Table 7-62.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13 | STRAP_LINK_LOSS_PASS_THRU | R | 0h | Link Loss Pass Through Enable Strap
0h = Enable 1h = Disable |
12 | STRAP_MIRROR_EN | R | 0h | Mirror Mode Enable StraP. Refer to strap configuration section as this strap also decides MAC interface in Bridge Mode applications.
0h = Disable 1h = Enable |
11-9 | STRAP_OPMODE | R | 0h | OPMODE Strap
0h = RGMII To Copper 1h = RGMII to 1000Base-X 2h = RGMII to 100Base-FX 3h = RGMII-SGMII Bridge 4h = 1000Base-T to 1000Base-X 5h = 100Base-T to 100Base-FX 6h = SGMII to Copper 7h = JTAG for Boundary Scan |
8-4 | STRAP_PHY_ADD | R | 0h | PHY Address Strap |
3-2 | STRAP_ANEGSEL | R | 0h | Auto Negotiation Mode Select Strap. Refer to Strap Configuration Section |
1 | STRAP_ANEG_EN | R | 0h | Auto Negotiation Enable Strap
0h = Enable 1h = Disable |
0 | RESERVED | R | 0h | Reserved |
DBG_PRBS_BYTE_CNT is shown in Table 7-63.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PRBS_BYTE_CNT | R | 0h | Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register DBG_PRBS_ERR_CNT bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF (see register 0x0016) |
DBG_PRBS_ERR_CNT is shown in Table 7-64.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10 | PRBS_PKT_CNT_OVF | R | 0h | If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1of this register |
9 | PRBS_BYTE_CNT_OVF | R | 0h | If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1of this register |
8 | RESERVED | R | 0h | Reserved |
7-0 | PRBS_ERR_CNT | R | 0h | Holds number of errored bytes that received by the PRBS checker. Value in this register is locked when write is done to bit[0] or bit[1] (see bellow). When PRBS Count Mode set to zero, count stops on 0xFF (see register 0x0016) Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters |
DBG_PKT_LEN_PRBS is shown in Table 7-65.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PKT_LEN_PRBS | R/W | 5DCh | Length (in bytes) of PRBS packets, this effect the PRBS packets and not |
DBG_IPG_LEN is shown in Table 7-66.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7-0 | IPG_LEN | R/W | 7Dh | Inter-packet gap (in 4 bytes) between PRBS packets. IPG increments in steps of 4 bytes |
ANA_RGMII_DLL_CTRL is shown in Table 7-67.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | DLL_EN_FORCE_VAL | R/W | 0h | If dll_en_force_en is set, this is the value of DLL_EN |
8 | DLL_EN_FORCE_CTRL | R/W | 0h | Force DLL_EN value |
7-4 | DLL_TX_DELAY_CTRL_SL | R/W | 7h | Steps of 250ps, affects the CLK_90 output. - same behavior as bit [3:0] |
3-0 | DLL_RX_DELAY_CTRL_SL | R/W | 7h | Steps of 250ps, affects the CLK_90 output.
b[3], b[2], b[1], b[0], shift, mode
please note - the actual delay is also effected by the shift mode in reg 0x32
3h = 1.0ns, Shift 5h = 1.5ns, Shift 7h = 2.0 ns, Shift(*) - default 9h = 2.5ns, Shift Bh = 3.0 ns,Shift Dh = 3.5ns, Shift Fh = 0ns, Align(**) |
ANA_PLL_PROG_PI is shown in Table 7-68.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RESERVED | R/W | 0h | Reserved |
SGMII_TESTMODE is shown in Table 7-69.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0h | Reserved |
14-13 | SGMII_TESTMODE_SWING | R/W | 0h | Voltage Swing Pk-Pk Typ (V)
0h = 1.100 (default) 1h = 1.280 2h = 0.920 3h = Do not use |
12-0 | RESERVED | R/W | 0h | Reserved |
DSP_HYBRID_CFG2 is shown in Table 7-70.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12-8 | RESERVED | R/W | 0h | Reserved |
7-5 | RESERVED | R/W | 0h | Reserved |
4-0 | RESERVED | R/W | 0h | Reserved |
LOOPCR is shown in Table 7-71.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | FB_AEQ_CNT | R/W | 7h | AEQ max number of fallbacks |
12-8 | AEQ_MAX_STEP | R/W | 7h | the max step in aeq table |
7-5 | AEQ_STEP_SIZE | R/W | 1h | increment step for aeq table |
4-1 | RESERVED | R | 0h | |
0 | AEQ_BEG | R/W | 0h | starting index for aeq table
0h = normal operation 1h = near-end loopback |
RXF_CFG is shown in Table 7-72.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | WOL_OUT_CLEAN | RH/WoP | 0h | If WOL out is in level mode in bit 8, writing to this bit will clear it. |
10-9 | WOL_OUT_STRETCH | R/W | 0h | If WOL out is in pulse mode in bit 8, this is the pulse length:
0h = 8 clock cycles 1h = 16 clock cycles 2h = 32 clock cycles 3h = 64 clock cycles |
8 | WOL_OUT_MODE | R/W | 0h | Mode of the wake up that goes to GPIO pin:
0h = Pulse Mode. 1h = Level Mode |
7 | ENHANCED_MAC_SUPPORT | R/W | 0h | Enables enhanced RX features. This bit should be set when using wakeup abilities, CRC check or RX 1588 indication |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | WAKE_ON_UCAST | R/W | 0h | If set, issue an interrupt upon reception of unicast packets |
3 | RESERVED | R/W | 0h | Reserved |
2 | WAKE_ON_BCAST | R/W | 0h | If set, issue an interrupt upon reception of broadcast packets |
1 | WAKE_ON_PATTERN | R/W | 0h | If set, issue an interrupt upon reception of a packet with configured pattern |
0 | WAKE_ON_MAGIC | R/W | 0h | If set, issue an interrupt upon reception of magic packet |
RXF_STATUS is shown in Table 7-73.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7 | SFD_ERR | RC | 0h | SFD Error Detected |
6 | BAD_CRC | RC | 0h | Bad CRC Packet Received |
5 | RESERVED | RC | 0h | Reserved |
4 | UCAST_RCVD | RC | 0h | Unicast Packet Received |
3 | RESERVED | RC | 0h | Reserved |
2 | BCAST_RCVD | RC | 0h | Broadcast Packet Received |
1 | PATTERN_RCVD | RC | 0h | Pattern Match Packet Received |
0 | MAGIC_RCVD | RC | 0h | Magic Packet Received |
RXF_PMATCH_DATA1 is shown in Table 7-74.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PMATCH_DATA_15_0 | R/W | 0h | Bits 15:0 of Perfect Match Data - used for DA (destination address) match |
RXF_PMATCH_DATA2 is shown in Table 7-75.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PMATCH_DATA_31_16 | R/W | 0h | Bits 31:16 of Perfect Match Data - used for DA (destination address) match |
RXF_PMATCH_DATA3 is shown in Table 7-76.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PMATCH_DATA_47_32 | R/W | 0h | Bits 47:32 of Perfect Match Data - used for DA (destination address) match |
RXF_SCRON_PASS1 is shown in Table 7-77.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | SCRON_PASSWORD_15_0 | R/W | 0h | Bits 15:0 of secure-on password (related to magic packet) |
RXF_SCRON_PASS2 is shown in Table 7-78.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | SCRON_PASSWORD_31_16 | R/W | 0h | Bits 31:16 of secure-on password (related to magic packet) |
RXF_SCRON_PASS3 is shown in Table 7-79.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | SCRON_PASSWORD_47_32 | R/W | 0h | Bits 47:32 of secure-on password (related to magic packet) |
RXF_PATTERN_1 is shown in Table 7-80.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_0_1 | R/W | 0h | Bytes 0 (LSbyte) + 1 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_2 is shown in Table 7-81.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_2_3 | R/W | 0h | Bytes 2 + 3 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_3 is shown in Table 7-82.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_4_5 | R/W | 0h | Bytes 4 + 5 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_4 is shown in Table 7-83.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_6_7 | R/W | 0h | Bytes 6 + 7 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_5 is shown in Table 7-84.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_8_9 | R/W | 0h | Bytes 8 + 9 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_6 is shown in Table 7-85.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_10_11 | R/W | 0h | Bytes 10 + 11 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_7 is shown in Table 7-86.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_12_13 | R/W | 0h | Bytes 12 + 13 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_8 is shown in Table 7-87.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_14_15 | R/W | 0h | Bytes 14 + 15 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_9 is shown in Table 7-88.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_16_17 | R/W | 0h | Bytes 16 + 17 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_10 is shown in Table 7-89.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_18_19 | R/W | 0h | Bytes 18 + 19 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_11 is shown in Table 7-90.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_20_21 | R/W | 0h | Bytes 20 + 21 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_12 is shown in Table 7-91.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_22_23 | R/W | 0h | Bytes 22 + 23 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_13 is shown in Table 7-92.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_24_25 | R/W | 0h | Bytes 24 + 25 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_14 is shown in Table 7-93.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_26_27 | R/W | 0h | Bytes 26 + 27 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_15 is shown in Table 7-94.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_28_29 | R/W | 0h | Bytes 28 + 29 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_16 is shown in Table 7-95.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_30_31 | R/W | 0h | Bytes 30 + 31 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_17 is shown in Table 7-96.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_32_33 | R/W | 0h | Bytes 32 + 33 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_18 is shown in Table 7-97.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_34_35 | R/W | 0h | Bytes 34 + 35 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_19 is shown in Table 7-98.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_36_37 | R/W | 0h | Bytes 36 + 37 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_20 is shown in Table 7-99.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_38_39 | R/W | 0h | Bytes 38 + 39 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_21 is shown in Table 7-100.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_40_41 | R/W | 0h | Bytes 40 + 41 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_22 is shown in Table 7-101.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_42_43 | R/W | 0h | Bytes 42 + 43 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_23 is shown in Table 7-102.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_44_45 | R/W | 0h | Bytes 44 + 45 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_24 is shown in Table 7-103.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_46_47 | R/W | 0h | Bytes 46 + 47 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_25 is shown in Table 7-104.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_48_49 | R/W | 0h | Bytes 48 + 49 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_26 is shown in Table 7-105.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_50_51 | R/W | 0h | Bytes 50 + 51 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_27 is shown in Table 7-106.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_52_53 | R/W | 0h | Bytes 52 + 53 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_28 is shown in Table 7-107.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_54_55 | R/W | 0h | Bytes 54 + 55 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_29 is shown in Table 7-108.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_56_57 | R/W | 0h | Bytes 56 + 57 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_30 is shown in Table 7-109.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_58_59 | R/W | 0h | Bytes 58 + 59 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_31 is shown in Table 7-110.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_60_61 | R/W | 0h | Bytes 60 + 61 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_32 is shown in Table 7-111.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_62_63 | R/W | 0h | Bytes 62 + 63 of the configured pattern. Each byte can be masked separately RXF_PATTERN_BYTE_MASK registers |
RXF_PATTERN_BYTE_MASK_1 is shown in Table 7-112.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_MASK_0_15 | R/W | 0h | Masks for bytes 0 to 15 of the pattern. For each byte: '1' means masked |
RXF_PATTERN_BYTE_MASK_2 is shown in Table 7-113.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_MASK_16_31 | R/W | 0h | Masks for bytes 16 to 31 of the pattern. For each byte: '1' means masked |
RXF_PATTERN_BYTE_MASK_3 is shown in Table 7-114.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_MASK_32_47 | R/W | 0h | Masks for bytes 32 to 47 of the pattern. For each byte: '1' means masked |
RXF_PATTERN_BYTE_MASK_4 is shown in Table 7-115.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PATTERN_BYTES_MASK_48_63 | R/W | 0h | Masks for bytes 48 to 63 of the pattern. For each byte: '1' means masked |
10M_SGMII_CFG is shown in Table 7-116.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7 | 10M_SGMII_RATE_ADAPT_DISABLE | R/W | 0h | Rate Adaption Disable
0h = Rate Adaption Enabled 1h = Rate Adaption Disabled |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3-0 | RESERVED | R/W | 0h | Reserved |
IO_MUX_CFG is shown in Table 7-117.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-8 | CLK_O_SEL | R/W | Ch | Select clock output source
0h = Channel A receive clock 1h = Channel B receive clock 2h = Channel C receive clock 3h = Channel D receive clock 4h = Channel A receive clock divided by 5 5h = Channel B receive clock divided by 5 6h = Channel C receive clock divided by 5 7h = Channel D receive clock divided by 5 8h = Channel A transmit clock 9h = Channel B transmit clock Ah = Channel C transmit clock Bh = Channel D transmit clock Ch = Reference clock (synchronous to XI input clock)Note: Reg 0xC6 must be set equal to 0x10 before CLK_O_SEL can be modified |
7 | RESERVED | R | 0h | Reserved |
6 | CLK_O_DISABLE | R/W | X | Clock Out Disable
0h = Clock Out Enable 1h = Clock Out Disable |
5 | RESERVED | R/W | 0h | Reserved |
4-0 | MAC_IMPEDANCE_CTRL | R/W | 10h | Impedance Control for MAC I/Os: Output impedance approximate range from 35-70 Ω in 32 steps. Lowest being 11111 and highest being 00000. Range and Step size will vary with process. Default is set to 50 Ω by trim but the default register value can vary by process. Non default values of MAC I/O impedance can be used based on trace impedance. Mismatch between device and trace impedance can cause voltage overshoot and undershoot. |
IO_MUX_GPIO_CTRL2 is shown in Table 7-118.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-8 | RESERVED | R | 0h | Reserved |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | RESERVED | R | 0h | Reserved |
TDR_GEN_CFG1 is shown in Table 7-119.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
12 | TDR_CH_CD_BYPASS | R/W | 0h | Bypass channel C and D in TDR tests |
11 | TDR_CROSS_MODE_DIS | R/W | 0h | If set, disable cross mode option - never check the cross (Listen only to the same channel you transmit) |
10 | TDR_NLP_CHECK | R/W | 1h | If set, check for NLPs during silence |
9-7 | TDR_AVG_NUM | R/W | 6h | Number Of TDR Cycles to Average: 000b = 1 TDR cycle 001b = 2 TDR cycles 010b = 4 TDR cycles 011b = 8 TDR cycles 100b = 16 TDR cycles 101b = 32 TDR cycles 110b = 64 TDR cycles (default) 111b = Reserved |
6-4 | TDR_SEG_NUM | R/W | 5h | Number of TDR segments to check |
3-0 | TDR_CYCLE_TIME | R/W | 2h | Number of micro-seconds in each TDR cycle |
TDR_GEN_CFG2 is shown in Table 7-120.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_SILENCE_TH | R/W | C8h | Energy detection threshold |
7-6 | TDR_POST_SILENCE_TIME | R/W | 1h | timer for tdr to look for energy after TDR transaction, if energy detected this is fail tdr |
5-4 | TDR_PRE_SILENCE_TIME | R/W | 1h | timer for tdr to look for energy before starting , if energy detected this is fail tdr |
3-0 | RESERVED | R | 0h | Reserved |
TDR_SEG_DURATION1 is shown in Table 7-121.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14-10 | TDR_SEG_DURATION_SEG3 | R/W | 14h | Number of 125MHz clock cycles to run for segment #3 |
9-5 | TDR_SEG_DURATION_SEG2 | R/W | 19h | Number of 125MHz clock cycles to run for segment #2 |
4-0 | TDR_SEG_DURATION_SEG1 | R/W | 6h | Number of 125MHz clock cycles to run for segment #1 |
TDR_SEG_DURATION2 is shown in Table 7-122.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_SEG_DURATION_SEG5 | R/W | A0h | Number of 125MHz clock cycles to run for segment #5 |
7-6 | RESERVED | R | 0h | Reserved |
5-0 | TDR_SEG_DURATION_SEG4 | R/W | 1Eh | Number of 125MHz clock cycles to run for segment #4 |
TDR_GEN_CFG3 is shown in Table 7-123.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | TDR_FWD_SHADOW_SEG4 | R/W | Eh | Indicates how much time to wait after max level before declaring we found a peak in segment #4 |
11-8 | TDR_FWD_SHADOW_SEG3 | R/W | 9h | Indicates how much time to wait after max level before declaring we found a peak in segment #3 |
7 | RESERVED | R | 0h | Reserved |
6-4 | TDR_FWD_SHADOW_SEG2 | R/W | 7h | Indicates how much time to wait after max level before declaring we found a peak in segment #2 |
3 | RESERVED | R | 0h | Reserved |
2-0 | TDR_FWD_SHADOW_SEG1 | R/W | 6h | Indicates how much time to wait after max level before declaring we found a peak in segment #1 |
TDR_GEN_CFG4 is shown in Table 7-124.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13-11 | TDR_SDW_AVG_LOC | R/W | 3h | how much to look between segments to search average peak |
10-9 | RESERVED | R | 0h | Reserved |
8 | TDR_TX_TYPE_SEG5 | R/W | 1h | the tx type (10/100) for this segment |
7 | TDR_TX_TYPE_SEG4 | R/W | 1h | the tx type (10/100) for this segment |
6 | TDR_TX_TYPE_SEG3 | R/W | 1h | the tx type (10/100) for this segment |
5 | TDR_TX_TYPE_SEG2 | R/W | 0h | the tx type (10/100) for this segment |
4 | TDR_TX_TYPE_SEG1 | R/W | 0h | the tx type (10/100) for this segment |
3-0 | TDR_FWD_SHADOW_SEG5 | R/W | Fh | Indicates how much time to wait after max level before declaring we found a peak in segment #5 |
TDR_PEAKS_LOC_A_0_1 is shown in Table 7-125.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_A_1 | R | 0h | Found peak location 1 in channel A |
7-0 | TDR_PEAKS_LOC_A_0 | R | 0h | Found peak location 0 in channel A |
TDR_PEAKS_LOC_A_2_3 is shown in Table 7-126.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_A_3 | R | 0h | Found peak location 3 in channel A |
7-0 | TDR_PEAKS_LOC_A_2 | R | 0h | Found peak location 2 in channel A |
TDR_PEAKS_LOC_A_4_B_0 is shown in Table 7-127.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_B_0 | R | 0h | Found peak location 0 in channel B |
7-0 | TDR_PEAKS_LOC_A_4 | R | 0h | Found peak location 4 in channel A |
TDR_PEAKS_LOC_B_1_2 is shown in Table 7-128.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_B_2 | R | 0h | Found peak location 2 in channel B |
7-0 | TDR_PEAKS_LOC_B_1 | R | 0h | Found peak location 1 in channel B |
TDR_PEAKS_LOC_B_3_4 is shown in Table 7-129.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_B_4 | R | 0h | Found peak location 4 in channel B |
7-0 | TDR_PEAKS_LOC_B_3 | R | 0h | Found peak location 3 in channel B |
TDR_PEAKS_LOC_C_0_1 is shown in Table 7-130.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_C_1 | R | 0h | Found peak location 1 in channel C |
7-0 | TDR_PEAKS_LOC_C_0 | R | 0h | Found peak location 0 in channel C |
TDR_PEAKS_LOC_C_2_3 is shown in Table 7-131.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_C_3 | R | 0h | Found peak location 3 in channel C |
7-0 | TDR_PEAKS_LOC_C_2 | R | 0h | Found peak location 2 in channel C |
TDR_PEAKS_LOC_C_4_D_0 is shown in Table 7-132.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_D_0 | R | 0h | Found peak location 0 in channel D |
7-0 | TDR_PEAKS_LOC_C_4 | R | 0h | Found peak location 4 in channel C |
TDR_PEAKS_LOC_D_1_2 is shown in Table 7-133.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_D_2 | R | 0h | Found peak location 2 in channel D |
7-0 | TDR_PEAKS_LOC_D_1 | R | 0h | Found peak location 1 in channel D |
TDR_PEAKS_LOC_D_3_4 is shown in Table 7-134.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TDR_PEAKS_LOC_D_4 | R | 0h | Found peak location 4 in channel D |
7-0 | TDR_PEAKS_LOC_D_3 | R | 0h | Found peak location 3 in channel D |
TDR_GEN_STATUS is shown in Table 7-135.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11 | TDR_P_LOC_CROSS_MODE_D | R | 0h | Peak found at cross mode in channel D |
10 | TDR_P_LOC_CROSS_MODE_C | R | 0h | Peak found at cross mode in channel C |
9 | TDR_P_LOC_CROSS_MODE_B | R | 0h | Peak found at cross mode in channel B |
8 | TDR_P_LOC_CROSS_MODE_A | R | 0h | Peak found at cross mode in channel A |
7 | TDR_P_LOC_OVERFLOW_D | R | 0h | Total number of peaks in current segment reached max value of 5 in channel D |
6 | TDR_P_LOC_OVERFLOW_C | R | 0h | Total number of peaks in current segment reached max value of 5 in channel C |
5 | TDR_P_LOC_OVERFLOW_B | R | 0h | Total number of peaks in current segment reached max value of 5 in channel B |
4 | TDR_P_LOC_OVERFLOW_A | R | 0h | Total number of peaks in current segment reached max value of 5 in channel A |
3 | TDR_SEG1_HIGH_CROSS_D | R | 0h | Peak crossed high threshold of segment #1 in channel D |
2 | TDR_SEG1_HIGH_CROSS_C | R | 0h | peak crossed high threshold of segment #1 in channel C |
1 | TDR_SEG1_HIGH_CROSS_B | R | 0h | peak crossed high threshold of segment #1 in channel B |
0 | TDR_SEG1_HIGH_CROSS_A | R | 0h | peak crossed high threshold of segment #1 in channel A |
TDR_PEAKS_SIGN_A_B is shown in Table 7-136.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | TDR_PEAKS_SIGN_B_4 | R | 0h | found peaks sign 4 in channel B |
8 | TDR_PEAKS_SIGN_B_3 | R | 0h | found peaks sign 3 in channel B |
7 | TDR_PEAKS_SIGN_B_2 | R | 0h | found peaks sign 2 in channel B |
6 | TDR_PEAKS_SIGN_B_1 | R | 0h | found peaks sign 1 in channel B |
5 | TDR_PEAKS_SIGN_B_0 | R | 0h | found peaks sign 0 in channel B |
4 | TDR_PEAKS_SIGN_A_4 | R | 0h | found peaks sign 4 in channel A |
3 | TDR_PEAKS_SIGN_A_3 | R | 0h | found peaks sign 3 in channel A |
2 | TDR_PEAKS_SIGN_A_2 | R | 0h | found peaks sign 2 in channel A |
1 | TDR_PEAKS_SIGN_A_1 | R | 0h | found peaks sign 1 in channel A |
0 | TDR_PEAKS_SIGN_A_0 | R | 0h | found peaks sign 0 in channel A |
TDR_PEAKS_SIGN_C_D is shown in Table 7-137.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | TDR_PEAKS_SIGN_D_4 | R | 0h | found peaks sign 4 in channel D |
8 | TDR_PEAKS_SIGN_D_3 | R | 0h | found peaks sign 3 in channel D |
7 | TDR_PEAKS_SIGN_D_2 | R | 0h | found peaks sign 2 in channel D |
6 | TDR_PEAKS_SIGN_D_1 | R | 0h | found peaks sign 1 in channel D |
5 | TDR_PEAKS_SIGN_D_0 | R | 0h | found peaks sign 0 in channel D |
4 | TDR_PEAKS_SIGN_C_4 | R | 0h | found peaks sign 4 in channel C |
3 | TDR_PEAKS_SIGN_C_3 | R | 0h | found peaks sign 3 in channel C |
2 | TDR_PEAKS_SIGN_C_2 | R | 0h | found peaks sign 2 in channel C |
1 | TDR_PEAKS_SIGN_C_1 | R | 0h | found peaks sign 1 in channel C |
0 | TDR_PEAKS_SIGN_C_0 | R | 0h | found peaks sign 0 in channel C |
DBG_PRBS_PKT_CNT_1 is shown in Table 7-138.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PRBS_PKT_CNT_15_0 | R | 0h | Holds bits [15:0] of number of total packets that received by the PRBS checker. Value in this register is locked when write is done to register DBG_PRBS_ERR_CNT bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF (see register 0x0016) |
DBG_PRBS_PKT_CNT_2 is shown in Table 7-139.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | PRBS_PKT_CNT_31_16 | R | 0h | Holds bits [31:16] of number of total packets that received by the PRBS checker. Value in this register is locked when write is done to register DBG_PRBS_ERR_CNT bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF (see register 0x0016) |
OP_MODE_DECODE is shown in Table 7-140.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0h | Reserved |
8-7 | RESERVED | R | 0h | Reserved |
6 | BRIDGE_MODE_RGMII_MAC | R/W | 1h | 0h = RGMII to SGMII Bridge 1h = SGMII to RGMII Bridge |
5 | RGMII_MII_SEL | R/W | 0h | 0h = RGMII 1h = MII |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2-0 | CFG_OPMODE | R/W | 0h | Operation Mode
0h = RGMII to Copper 1h = RGMII to 1000Base-X 2h = RGMII to 100Base-FX 3h = RGMII to SGMII 4h = 1000Base-T to 1000Base-X 5h = 100Base-T to 100Base-FX 6h = SGMII to Copper 7h = Reserved |
GPIO_MUX_CTRL is shown in Table 7-141.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R/W | 0h | Reserved |
11-8 | RESERVED | R/W | 0h | Reserved |
7-4 | JTAG_TDO_GPIO_1_CTRL | R/W | 7h | See bits [3:0] for GPIO control options. If either type of SFD is enabled, this pin will be automatically configured to TX_SFD. |
3-0 | LED_2_GPIO_0_CTRL | R/W | Ah | Following options are available for GPIO control. If either type of SFD is enabled, this pin will be automatically configured to RX_SFD.
0h = CLK_OUT 1h = RESERVED 2h = INT 3h = Link status 4h = RESERVED 5h = Transmit SFD 6h = Receive SFD 7h = WOL 8h = Energy detect(1000Base-T and 100Base-TX only) 9h = PRBS errors Ah = LED_2 Bh = LED_GPIO(3) Ch = CRS Dh = COL Eh = constant '0' Fh = constant '1' |
MC_LINK_LOSS is shown in Table 7-142.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R/W | 0h | Reserved |
12-9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2-1 | RESERVED | R/W | 0h | Reserved |
0 | CFG_NO_LINK_LINK_LOSS_EN | R/W | 1h | Disables MC link_loss feature when there is no_link for given time.
0h = Enable link loss feature 1h = Disable link loss feature |
FX_CTRL is shown in Table 7-143.
Return to the Summary Table.
Registers after 0xC00 are common for Fiber, SGMII IP blocks for RGMII-to-SGMII, SGMII-to-RGMII, and Media Convertor.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | CTRL0_RESET | R/W | 0h | Controls reset in Fiber mode. This bit is automatically cleared after reset is completed.
0h = Normal Operation 1h = Reset. |
14 | CTRL0_LOOPBACK | R/W | 0h | 100BASE-X, 1000BASE-FX and RGMII-SGMII, SGMII-RGMII MAC loopback.
0h = Disable MAC loopback 1h = Enable MAC Loopback |
13 | CTRL0_SPEED_SEL_LSB | R/W | 0h | Speed selection bits LSB[13] and MSB[6] are used to control the data rate of the ethernet link when in Fiber Ethernet mode. These bits are also affected by straps.
0h = 10Mbps 1h = 100Mbps 2h = 1000Mbps 3h = Reserved |
12 | CTRL0_ANEG_EN | R/W | 1h | Enable 1000BASE-X, R2S, S2R Bridge mode Auto-negotiation. Controlled by strap.
0h = Disable 1h = Enable |
11 | CTRL0_PWRDN | R/W | 0h | Power Down SGMII for R2S, S2R, 1000BX, 100FX. Digital is in reset.
0h = Normal operation 1h = Power Down |
10 | CTRL0_ISOLATE | R/W | 0h | Isolate MAC interface. Used in 1000BX, 100FX and RGMII-SGMII mode. N/A in SGMII-RGMII mode.
0h = Normal operation 1h = Isolate |
9 | CTRL0_RESTART_AN | R/W | 0h | Writing 1 to this control bit restarts Autoneg in SGMII and 1000B-X mode. It is self-cleared by hardware.
0h = Normal operation 1h = Restart 1000BASE-X/SGMII Auto-Negotiation Process |
8 | CTRL0_DUPLEX_MODE | R/W | 1h | Forced Duplex mode. Applicable only in MII-100FX mode.
0h = Half duplex mode 1h = Full duplex mode |
7 | CTRL0_COL_TEST | R/W | 0h | Used to test collision functionality. Settings this bit asserts collision on just asserting tx_en |
6 | CTRL0_SPEED_SEL_MSB | R/W | 1h | Forced Speed for SGMII only when Autoneg is disabled. Controlled by straps. See bit 13 of this register. |
5-0 | RESERVED | R/W | 0h | Reserved |
FX_STS is shown in Table 7-144.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | STTS_100B_T4 | R | 0h | Return Always 0. Device doesn 't support 100BASE-T4 mode |
14 | STTS_100B_X_FD | R | 1h | Return Always 1. Device supports 100BASE-FX Full-Duplex |
13 | STTS_100B_X_HD | R | 1h | Return Always 1. Device supports 100BASE-FX Half-Duplex |
12 | STTS_10B_FD | R | 0h | Return Always 0. Device doesn 't support 10Mbps fiber mode |
11 | STTS_10B_HD | R | 0h | Return Always 0. Device doesn 't support 10Mbps fiber mode |
10 | STTS_100B_T2_FD | R | 0h | Return Always 0. Device doesn 't support 100BASE-T2 mode |
9 | STTS_100B_T2_HD | R | 0h | Return Always 0. Device doesn 't support 100BASE-T2 mode |
8 | STTS_EXTENDED_STATUS | R | 1h | Return Always 1. Extended status information in register15 |
7 | RESERVED | R | 0h | Reserved |
6 | STTS_MF_PREAMBLE_SUPRSN | R | 1h | Return Always 1. Phy accepts management frames with preamble suppressed. |
5 | STTS_ANEG_COMPLETE | R | 0h | 1: Auto negotiation process complete 0:Auto negotiation process not complete |
4 | STTS_REMOTE_FAULT | R | 0h | 1: Remote fault condition detected 0:Remote fault condition not detected |
3 | STTS_ANEG_ABILITY | R | 1h | Return Always 1. Device capable of performing Auto-Negotiation |
2 | STTS_LINK_STATUS | R | 0h | 1: link-up
0: link down
Indicates 100FX link-up in 100FX and 100FX MC Mode. Indicates 1000X link-up in 1000X and 1000X MC mode. In RGMII-SGMII mode, it indicates SGMII link-up and LP link up if Autoneg is enabled else(if autoneg disabled) it indicates SGMII link-up. In SGMII-RGMII mode, it indicates LP link-up |
1 | STTS_JABBER_DET | R | 0h | Return 0. |
0 | STTS_EXTENDED_CAPABILITY | R | 1h | Return Always 1. Device supports Extended register capabilities |
FX_PHYID1 is shown in Table 7-145.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13-0 | OUI_6_19_FIBER | R | 2000h | Organizationally Unique Identifier Bits 19:6 |
FX_PHYID2 is shown in Table 7-146.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | OUI_0_5_FIBER | R | 28h | Organizationally Unique Identifier Bits 5:0 |
9-4 | MODEL_NUM_FIBER | R | Fh | model number |
3-0 | REVISION_NUM_FIBER | R | 1h | revision number |
FX_ANADV is shown in Table 7-147.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | BP_NEXT_PAGE | R/W | 0h | Set this bit if next page needs to be advertised. 1 = Advertise 0 = Not advertised |
14 | BP_ACK | R | 0h | Always return 0 |
13-12 | BP_REMOTE_FAULT | R/W | 0h | 00 = LINK_OK 01=OFFLINE 10=LINK_FAILURE 11=AUTO_ERROR |
11-9 | RESERVED | R | 0h | Reserved |
8 | BP_ASYMMETRIC_PAUSE | R/W | 0h | 1 = Asymmetric Pause 0 = No asymmetric Pause |
7 | BP_PAUSE | R/W | 0h | 1 = MAC PAUSE 0 = No MAC PAUSE |
6 | BP_HALF_DUPLEX | R/W | 0h | 1 = Advertise 0 = Not advertised |
5 | BP_FULL_DUPLEX | R/W | 1h | 1 = Advertise 0 = Not advertised |
4-0 | BP_RSVD1 | R | 0h | Reserved. Set to 00000 |
FX_LPABL is shown in Table 7-148.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LP_ABILITY_NEXT_PAGE | R | 0h | 0h = LP is not capable of next page 1h = LP is capable of next page |
14 | LP_ABILITY_ACK | R | 0h | 0h = LP has not acknowledged that it has received link code word 1h = LP acknowledges that it has received link code word |
13-12 | LP_ABILITY_REMOTE_FAULT | R | 0h | Received Remote fault from LP.
0h = LINK_OK 1h = OFFLINE 2h = LINK_FAILURE 3h = AUTO_ERROR |
11-9 | RESERVED | R | 0h | Reserved |
8 | LP_ABILITY_ASYMMETRIC_PAUSE | R | 0h | 0h = LP does not request asymmetric pause 1h = LP requests of asymmetric pause |
7 | LP_ABILITY_PAUSE | R | 0h | 0h = LP is not capable of pause operation 1h = LP is capable of pause operation |
6 | LP_ABILITY_HALF_DUPLEX | R | 0h | 0h = LP is not 1000BASE-X Half-duplex capable 1h = LP is 1000BASE-X Half-duplex capable |
5 | LP_ABILITY_FULL_DUPLEX | R | 0h | 0h = LP is not 1000BASE-X Full-duplex capable 1h = LP is 1000BASE-X Full-duplex capable |
4-0 | RESERVED | R | 0h | Reserved |
FX_ANEXP is shown in Table 7-149.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | AN_EXP_LP_NEXT_PAGE_ABLE | R | 0h | 1: Link partner is Next page able 0: Link partner is not next page able Bit is set to 1 when device receives base page with NP bit (bit 15) set to 1. It is cleared when Autoneg state goes to AN_ENABLE. It is expected that NP bit will be set to 0 in SGMII mode as SGMII doesn 't supports next page. |
2 | AN_EXP_LOCAL_NEXT_PAGE_ABLE | R | 0h | 1 : Local device is next page able 0 : Local device is not next page able This bit is set to 1 in fiber 1000BASE-X mode. it is set to 0 in SGMII mode. |
1 | AN_EXP_PAGE_RECEIVED | R | 0h | 1 : A new page(base page or next page) has been received 0 : No new page has been received Status is latched when new page is received by the device. It is cleared when SW reads this register. |
0 | AN_EXP_LP_AUTO_NEG_ABLE | R | 0h | 1: Link partner is auto negotiation able 0: Link partner is not auto negotiation able Bit is set to 1 when device receives base page. It is cleared when Autoneg state goes to AN_ENABLE. |
FX_LOCNP is shown in Table 7-150.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NP_TX_NEXT_PAGE | R/W | 0h | 0: if last page 1: if there is more pages to transmit |
14 | RESERVED | R | 0h | Reserved |
13 | NP_TX_MESSAGE_PAGE_MODE | R/W | 1h | 0: unformatted page 1: message page |
12 | NP_TX_ACK_2 | R/W | 0h | device has the ability to comply with the message 0: cannot comply with message. 1: comply with message. |
11 | NP_TX_TOGGLE | R | 0h | 0: previous value of the transmitted link codeword equalled logic one. 1: previous value of the transmitted link codeword equalled logic zero |
10-0 | NP_TX_MESSAGE_FIELD | R/W | 1h | Message code field as defined in IEEE Annex 28C |
FX_LPNP is shown in Table 7-151.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LP_NP_NEXT_PAGE | R | 0h | LP last page 0: if last page 1: if there is more pages to transmit |
14 | LP_NP_ACK | R | 0h | Reserved |
13 | LP_NP_MESSAGE_PAGE_MODE | R | 0h | LP message page mode 0: unformatted page 1: message page |
12 | LP_NP_ACK_2 | R | 0h | LP has the ability to comply with the message 0: cannot comply with message. 1: comply with message. |
11 | LP_NP_TOGGLE | R | 0h | LP Toggle bit 0: previous value of the transmitted link codeword equalled logic one. 1: previous value of the transmitted link codeword equalled logic zero |
10-0 | LP_NP_MESSAGE_FIELD | R | 0h | LP Message code field as defined in IEEE Annex 28C |
CFG_FX_CTRL0 is shown in Table 7-152.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | RESERVED |
9 | CFG_SDIN | R/W | 0h | 0h = Use Signal Detect Pin 1h = Signal Detect Pin is not used |
8-0 | RESERVED | R | 0h | RESERVED |
FX_INT_EN is shown in Table 7-153.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | FEF_FAULT_EN | R/W | 1h | FEF fault received interrupt enable
0h = Disable Interrupt 1h = Enable Interrupt |
8 | TX_FIFO_FULL_EN | R/W | 1h | Fiber and SGMII Tx FIFO full interrupt enable
0h = Disable Interrupt 1h = Enable Interrupt |
7 | TX_FIFO_EMPTY_EN | R/W | 1h | Fiber and SGMII Tx FIFO empty interrupt enable
0h = Disable Interrupt 1h = Enable Interrupt |
6 | RX_FIFO_FULL_EN | R/W | 1h | Fiber and SGMII Rx FIFO full interrupt enable
0h = Disable Interrupt 1h = Enable Interrupt |
5 | RX_FIFO_EMPTY_EN | R/W | 1h | Fiber and SGMII Rx FIFO empty interrupt enable
0h = Disable Interrupt 1h = Enable Interrupt |
4 | LINK_STS_CHANGE_EN | R/W | 1h | Link Status Change Interrupt Enable
0h = Disable Interrupt 1h = Enable Interrupt |
3 | LP_FAULT_RX_EN | R/W | 1h | Link Partner Remote Fault Interrupt Enable
0h = Disable Interrupt 1h = Enable Interrupt |
2 | PRI_RES_FAIL_EN | R/W | 1h | Priority Resolution Fail Interrupt Enable
0h = Disable Interrupt 1h = Enable Interrupt |
1 | LP_NP_RX_EN | R/W | 1h | Link Partner Next Page Received Interrupt Enable
0h = Disable Interrupt 1h = Enable Interrupt |
0 | LP_BP_RX_EN | R/W | 1h | Link Partner Base Page Received Interrupt Enable
0h = Disable Interrupt 1h = Enable Interrupt |
FX_INT_STS is shown in Table 7-154.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | FEF_FAULT | RC | 0h | FEF fault received interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
8 | TX_FIFO_FULL | RC | 0h | Fiber Tx FIFO full interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
7 | TX_FIFO_EMPTY | RC | 0h | Fiber Tx FIFO empty interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
6 | RX_FIFO_FULL | RC | 0h | Fiber Rx FIFO full interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
5 | RX_FIFO_EMPTY | RC | 0h | Fiber Rx FIFO empty interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
4 | LINK_STS_CHANGE | RC | 0h | Link Status Change Interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
3 | LP_FAULT_RX | RC | 0h | Link Partner Remote Fault Interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
2 | PRI_RES_FAIL | RC | 0h | Priority Resolution Fail Interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
1 | LP_NP_RX | RC | 0h | Link Partner Next Page Received Interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |
0 | LP_BP_RX | RC | 0h | Link Partner Base Page Received Interrupt
0h = No Interrupt pending 1h = Interrupt pending, cleared on read |