SNLS614B September   2018  – December 2022 DP83869HM

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  WoL (Wake-on-LAN) Packet Detection
        1. 9.3.1.1 Magic Packet Structure
        2. 9.3.1.2 Magic Packet Example
        3. 9.3.1.3 Wake-on-LAN Configuration and Status
      2. 9.3.2  Start of Frame Detect for IEEE 1588 Time Stamp
        1. 9.3.2.1 SFD Latency Variation and Determinism
          1. 9.3.2.1.1 1000-Mb SFD Variation in Master Mode
          2. 9.3.2.1.2 1000-Mb SFD Variation in Slave Mode
          3. 9.3.2.1.3 100-Mb SFD Variation
      3. 9.3.3  Clock Output
      4. 9.3.4  Loopback Mode
        1. 9.3.4.1 Near-End Loopback
          1. 9.3.4.1.1 MII Loopback
          2. 9.3.4.1.2 PCS Loopback
          3. 9.3.4.1.3 Digital Loopback
          4. 9.3.4.1.4 Analog Loopback
          5. 9.3.4.1.5 External Loopback
          6. 9.3.4.1.6 Far-End (Reverse) Loopback
        2.       39
      5. 9.3.5  BIST Configuration
      6. 9.3.6  Interrupt
      7. 9.3.7  Power-Saving Modes
        1. 9.3.7.1 IEEE Power Down
        2. 9.3.7.2 Active Sleep
        3. 9.3.7.3 Passive Sleep
      8. 9.3.8  Mirror Mode
      9. 9.3.9  Speed Optimization
      10. 9.3.10 Cable Diagnostics
        1. 9.3.10.1 TDR
      11. 9.3.11 Fast Link Drop
      12. 9.3.12 Jumbo Frames
    4. 9.4 Device Functional Modes
      1. 9.4.1  Copper Ethernet
        1. 9.4.1.1 1000BASE-T
        2. 9.4.1.2 100BASE-TX
        3. 9.4.1.3 10BASE-Te
      2. 9.4.2  Fiber Ethernet
        1. 9.4.2.1 1000BASE-X
        2. 9.4.2.2 100BASE-FX
      3. 9.4.3  Serial GMII (SGMII)
      4. 9.4.4  Reduced GMII (RGMII)
        1. 9.4.4.1 1000-Mbps Mode Operation
        2. 9.4.4.2 1000-Mbps Mode Timing
        3. 9.4.4.3 10- and 100-Mbps Mode
      5. 9.4.5  Media Independent Interface (MII)
      6. 9.4.6  Bridge Modes
        1. 9.4.6.1 RGMII-to-SGMII Mode
        2. 9.4.6.2 SGMII-to-RGMII Mode
        3.       69
      7. 9.4.7  Media Convertor Mode
      8. 9.4.8  Register Configuration for Operational Modes
        1. 9.4.8.1 RGMII-to-Copper Ethernet Mode
        2. 9.4.8.2 RGMII-to-1000Base-X Mode
        3. 9.4.8.3 RGMII-to-100Base-FX Mode
        4. 9.4.8.4 RGMII-to-SGMII Bridge Mode
        5. 9.4.8.5 1000M Media Convertor Mode
        6. 9.4.8.6 100M Media Convertor Mode
        7. 9.4.8.7 SGMII-to-Copper Ethernet Mode
      9. 9.4.9  Serial Management Interface
        1. 9.4.9.1 Extended Address Space Access
          1. 9.4.9.1.1 Write Address Operation
          2. 9.4.9.1.2 Read Address Operation
          3. 9.4.9.1.3 Write (No Post Increment) Operation
          4. 9.4.9.1.4 Read (No Post Increment) Operation
          5. 9.4.9.1.5 Write (Post Increment) Operation
          6. 9.4.9.1.6 Read (Post Increment) Operation
          7. 9.4.9.1.7 Example of Read Operation Using Indirect Register Access
          8. 9.4.9.1.8 Example of Write Operation Using Indirect Register Access
      10. 9.4.10 Auto-Negotiation
        1. 9.4.10.1 Speed and Duplex Selection - Priority Resolution
        2. 9.4.10.2 Master and Slave Resolution
        3. 9.4.10.3 Pause and Asymmetrical Pause Resolution
        4. 9.4.10.4 Next Page Support
        5. 9.4.10.5 Parallel Detection
        6. 9.4.10.6 Restart Auto-Negotiation
        7. 9.4.10.7 Enabling Auto-Negotiation Through Software
        8. 9.4.10.8 Auto-Negotiation Complete Time
        9. 9.4.10.9 Auto-MDIX Resolution
    5. 9.5 Programming
      1. 9.5.1 Strap Configuration
        1. 9.5.1.1 Straps for PHY Address
        2. 9.5.1.2 Strap for DP83869HM Functional Mode Selection
        3. 9.5.1.3 LED Default Configuration Based on Device Mode
        4. 9.5.1.4 Straps for RGMII/SGMII to Copper
        5. 9.5.1.5 Straps for RGMII to 1000Base-X
        6. 9.5.1.6 Straps for RGMII to 100Base-FX
        7. 9.5.1.7 Straps for Bridge Mode (SGMII-RGMII)
        8. 9.5.1.8 Straps for 100M Media Convertor
        9. 9.5.1.9 Straps for 1000M Media Convertor
      2. 9.5.2 LED Configuration
      3. 9.5.3 Reset Operation
        1. 9.5.3.1 Hardware Reset
        2. 9.5.3.2 IEEE Software Reset
        3. 9.5.3.3 Global Software Reset
        4. 9.5.3.4 Global Software Restart
    6. 9.6 Register Maps
      1. 9.6.1 DP83869 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Copper Ethernet Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Clock Input
            1. 10.2.1.2.1.1 Crystal Recommendations
            2. 10.2.1.2.1.2 External Clock Source Recommendation
          2. 10.2.1.2.2 Magnetics Requirements
            1. 10.2.1.2.2.1 Magnetics Connection
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Fiber Ethernet Typical Ethernet
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Transceiver Connections
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Two-Supply Configuration
    2. 11.2 Three-Supply Configuration
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
        1. 12.1.1.1 MAC Interface Layout Guidelines
          1. 12.1.1.1.1 SGMII Layout Guidelines
          2. 12.1.1.1.2 RGMII Layout Guidelines
        2. 12.1.1.2 MDI Layout Guidelines
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

Figure 7-1 RGZ Package(48-Pin VQFN)Top View
Table 7-1 RGZ Package (VQFN) Pin Functions
PINI/OTYPEDESCRIPTION
NO.NAME
1TD_P_AI/OAnalogDifferential Transmit and Receive Signals
2TD_M_AI/OAnalogDifferential Transmit and Receive Signals
3VDDA2P5IPower2.5-V Analog Supply (+/-5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
4TD_P_BI/OAnalogDifferential Transmit and Receive Signals
5TD_M_BI/OAnalogDifferential Transmit and Receive Signals
6VDD1P1IPower1.1-V Digital Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
7TD_P_CI/OAnalogDifferential Transmit and Receive Signals
8TD_M_CI/OAnalogDifferential Transmit and Receive Signals
9VDDA2P5IPower2.5-V Analog Supply (+/-5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
10TD_P_DI/OAnalogDifferential Transmit and Receive Signals
11TD_M_DI/OAnalogDifferential Transmit and Receive Signals
12RBIASI—Bias Resistor Connection. An 11 kΩ +/-1% resistor should be connected from RBIAS to GND.
13VDDA1P8_1IPowerNo external supply is required for this pin in two-supply mode. When unused, no connections should be made to these pins. In three-supply mode, an external 1.8V(+/-5%) supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND.
14SONOAnalogDifferential SGMII or Fiber Data Output: This signal carries data from the PHY to the MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin provides LVDS signals, additional components may be required for the optical transceiver.
15SOPOAnalogDifferential SGMII or Fiber Data Output: This signal carries data from the PHY to the MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin provides LVDS signals, additional components may be required for the optical transceiver
16SIPIAnalogDifferential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin accepts LVDS signals, additional components may be required for the optical transceiver
17SINIAnalogDifferential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin accepts LVDS signals, additional components may be required for the optical transceiver
18VDDIOIPowerI/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND
19XOOClockCRYSTAL OSCILLATOR OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if a clock oscillator is used.
20XIIClockCRYSTAL OSCILLATOR INPUT: 25 MHz oscillator or crystal input.
21JTAG_CLK/TX_ERIWPUJTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity.
MII Mode: In MII mode, this pin will be configured as TX_ER pin and will be sourced from MAC to PHY. Use of this pin is optional.
22JTAG_TDO/GPIO_1O—JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device via TDO.
General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
23JTAG_TMSIWPUJTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. It is recommended to apply 3 clock cycles with JTAG_TMS high to reset the JTAG.
24JTAG_TDI/SDIWPUJTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device via TDI. SD: In 1000Base-X and 100Base-FX mode, this pin will act as Signal Detect. This should be connected to Signal Detect of optical transceiver.
25TX_D3IWPDTRANSMIT DATA: Signal TX_D[3:0] carries data from the MAC to the PHY in RGMII mode and MII mode. Data is synchronous to the transmit clock. In RGMII mode GTX_CLK is the transmit clock and in MII mode TX_CLK is the transmit clock.
26TX_D2IWPD
27TX_D1IWPD
28TX_D0IWPD
29GTX_CLK/TX_CLKI/OWPDRGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz in 1000 Mbps mode. This pin will be Input in RGMII mode.
MII TRANSMIT CLOCK: In MII mode, this pin provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. This pin will be output in MII mode. This pin will be GTX_CLK by default and can be changed to TX_CLK by register configurations.
30VDDIOIPowerI/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND
31VDD1P1IPower1.1-V Digital Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
32RX_CLKOStrap, WPDRECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 125 MHz in 1000 Mbps RGMII mode.
33RX_D0OStrap, WPDRECEIVE DATA: Signal RX_D[3:0] carries data from the PHY to the MAC in RGMII mode and in MII mode. Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK.
34RX_D1OStrap, WPD
35RX_D2OStrap, WPD
36RX_D3OStrap, WPD
37TX_CTRL/TX_ENIWPDTRANSMIT CONTROL: In RGMII mode, TX_CTRL combines the transmit enable and the transmit error signal inputs from the MAC using both clock edges.
TX_EN: In MII mode, this pin will function as TX_EN.
38RX_CTRL/RX_DVOWPDRECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).
RX_DV: In MII mode, this pin will function as RX_DV.
39VDD1P1IPower1.1-V Digital Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
40CLK_OUTOClockCLOCK OUTPUT: Output clock
41MDIOI/O—MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the management station or the PHY. This open-drain pin requires a 1.5kΩ pull-up resistor.
42MDCI—MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz. There is no minimum clock rate.
43RESET_NI—RESET_N: This pin is an active-low reset input that initializes or re-initializes all the internal registers of the DP83869. Asserting this pin low for at least 1µs will force a reset process to occur. It is in IO voltage domain. A 100Ω resistor and 47uF capacitor are required to be connected in series between RESET_N pin and Ground.
44INT_N/PWDN_NI/O—INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN.
POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode the device powers down and consumes minimum power. Register access is available through the Management Interface to configure and power up the device.
INTERRUPT: The interrupt pin is an open-drain, active low output signal indicating an interrupt condition has occurred. Register access is required to determine which event caused the interrupt. TI recommends using an external 2.2-kΩ resistor connected to the VDDIO supply. When register access is disabled through pin option, the interrupt will be asserted for 500ms before self-clearing.
45LED_2/GPIO_0I/OStrap, WPDLED_2: Part of VIO voltage domain.
General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
46LED_1/RX_EROStrap, WPDLED_1: Part of VIO voltage domain.
MII Mode: In MII mode this pin will be configured as RX_ER. This pin is asserted high synchronously to rising edge of RX_CLK. Use of this pin is optional.
47LED_0OStrap, WPDLED_0: This pin is part of the VDDIO voltage domain
48VDDA1P8_2IPowerNo external supply is required for this pin in two-supply mode. When unused, no connections should be made to these pins. In three-supply mode, an external 1.8V(+/-5%) supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND.

Pin Functionality definitions are given below:

  • I: Input
  • O: Output
  • I/O: Input/Output
  • Strap: Multifunctional bootstrap pins
  • WPD: Weak Pull Down Resistor (internal)
  • WPU: Weak Pull Up Resistor (internal)
  • Power: Power Supply Pins
  • Analog: Analog pins
Table 7-2 Pin States-1
PIN NO PIN NAME RESET COPPER MODE
MII RGMII SGMII
PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z
14 SON O Hi-Z O Hi-Z O Hi-Z O 50Ω
15 SOP O Hi-Z O Hi-Z O Hi-Z O 50Ω
16 SIP I Hi-Z I Hi-Z I Hi-Z I 50Ω
17 SIN I Hi-Z I Hi-Z I Hi-Z I 50Ω
21 JTAG_CLK/ TX_ER I PU I PU I PU I PU
22 JTAG_TDO / GPIO_1 I PD O Hi-Z O Hi-Z O Hi-Z
23 JTAG_TMS I PU I PU I PU I PU
24 JTAG_TDI / SD I PU I PU I PU I PU
25 TX_D3 I PD I PD I PD I PD
26 TX_D2 I PD I PD I PD I PD
27 TX_D1 I PD I PD I PD I PD
28 TX_D0 I PD I PD I PD I PD
29 GTX_CLK / TX_CLK I PD O PD I PD I PD
32 RX_CLK I PD O Hi-Z O (125MHz) Hi-Z I PD
33 RX_D0 I PD O Hi-Z O Hi-Z I PD
34 RX_D1 I PD O Hi-Z O Hi-Z I PD
35 RX_D2 I PD O Hi-Z O Hi-Z I PD
36 RX_D3 I PD O Hi-Z O Hi-Z I PD
37 TX_CTRL / TX_EN I PD I PD I PD I PD
38 RX_CTRL / RX_DV I PD O Hi-Z O Hi-Z I Hi-Z
40 CLK_OUT O (25MHz) Hi-Z O (25MHz) Hi-Z O (25MHz) Hi-Z O (25MHz) Hi-Z
41 MDIO I Hi-Z I/O Hi-Z I/O Hi-Z I/O Hi-Z
42 MDC I Hi-Z I Hi-Z I Hi-Z I Hi-Z
43 RESET_N I PU I PU I PU I PU
44 INT_N / PWDN_N I PU I/O PU/OD-PU I/O PU/OD-PU I/O PU/OD-PU
45 LED_2 / GPIO_0 I PD I/O Hi-Z I/O Hi-Z I/O Hi-Z
46 LED_1 / RX_ER I PD O Hi-Z O Hi-Z O Hi-Z
47 LED_0 I PD O Hi-Z O Hi-Z O Hi-Z
Table 7-3 Pin States-2
PIN NO PIN NAME MEDIA CONVERTOR BRIDGE MODE
RGMII TO SGMII SGMII TO RGMII
PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z
14 SON O 50Ω O 50Ω O 50Ω
15 SOP O 50Ω O 50Ω O 50Ω
16 SIP I 50Ω I 50Ω I 50Ω
17 SIN I 50Ω I 50Ω I 50Ω
21 JTAG_CLK/ TX_ER I PU I PU I PU
22 JTAG_TDO / GPIO_1 O Hi-Z O Hi-Z O Hi-Z
23 JTAG_TMS I PU I PU I PU
24 JTAG_TDI / SD I PU I PU I PU
25 TX_D3 I PD I PD I PD
26 TX_D2 I PD I PD I PD
27 TX_D1 I PD I PD I PD
28 TX_D0 I PD I PD I PD
29 GTX_CLK / TX_CLK I PD I PD I PD
32 RX_CLK I PD O Hi-Z O Hi-Z
33 RX_D0 I PD O Hi-Z O Hi-Z
34 RX_D1 I PD O Hi-Z O Hi-Z
36 RX_D2 I PD O Hi-Z O Hi-Z
36 RX_D3 I PD O Hi-Z O Hi-Z
37 TX_CTRL / TX_EN I PD I PD I PD
38 RX_CTRL / RX_DV I PD O Hi-Z O Hi-Z
40 CLK_OUT O (25MHz) Hi-Z O (25MHz) Hi-Z O (25MHz) Hi-Z
41 MDIO I/O Hi-Z I/O Hi-Z I/O Hi-Z
42 MDC I Hi-Z I Hi-Z I Hi-Z
43 RESET_N I PU I PU I PU
44 INT_N / PWDN_N I/O PU/OD-PU I/O PU/OD-PU I/O PU/OD-PU
45 LED_2 / GPIO_0 I/O Hi-Z I/O Hi-Z I/O Hi-Z
46 LED_1 / RX_ER O Hi-Z O Hi-Z O Hi-Z
47 LED_0 O Hi-Z O Hi-Z O Hi-Z
Table 7-4 Pin States-3
PIN NO PIN NAME IEEE PWDN MII ISOLATE
PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z
14 SON O 50Ω O 50Ω
15 SOP O 50Ω O 50Ω
16 SIP I 50Ω I 50Ω
17 SIN I 50Ω I 50Ω
21 JTAG_CLK/ TX_ER I/O PU I PU
22 JTAG_TDO / GPIO_1 O Hi-Z O Hi-Z
23 JTAG_TMS I PU I PU
24 JTAG_TDI / SD I PU I PU
25 TX_D3 I PD I PD
26 TX_D2 I PD I PD
27 TX_D1 I PD I PD
28 TX_D0 I PD I PD
29 GTX_CLK / TX_CLK I PD I PD
32 RX_CLK O (2.5MHz) Hi-Z I PD
33 RX_D0 O Hi-Z I PD
34 RX_D1 O Hi-Z I PD
36 RX_D2 O Hi-Z I PD
36 RX_D3 O Hi-Z I PD
37 TX_CTRL / TX_EN I PD I PD
38 RX_CTRL / RX_DV O Hi-Z I PD
40 CLK_OUT O (25MHz) Hi-Z O (25MHz) Hi-Z
41 MDIO I Hi-Z I Hi-Z
42 MDC I Hi-Z I Hi-Z
43 RESET_N I PD I PU
44 INT_N / PWDN_N I/O PU/OD-PU I/O PU/OD-PU
45 LED_2 / GPIO_0 O Hi-Z O Hi-Z
46 LED_1 / RX_ER O Hi-Z O Hi-Z
47 LED_0 O Hi-Z O Hi-Z