SLVSBN6A June   2013  – August 2015 DRV201A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VCM Driver Output Stage Operation
      2. 7.3.2 Ringing Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
        1. 7.5.1.1 Single Write to a Defined Location
        2. 7.5.1.2 Single Read from a Defined Location and Current Location
        3. 7.5.1.3 Sequential Read and Write
        4. 7.5.1.4 I2C Device Address, Start and Stop Condition
    6. 7.6 Register Maps
      1. 7.6.1 Control Register (Address - 0x02h)
      2. 7.6.2 VCM MSB Current Control Register (VCM_Current_MSB) Address - 0x03h
      3. 7.6.3 VCM LSB Current Control Register (VCM_Current_lSB) Address - 0x04h
      4. 7.6.4 Status Register (Status) Address - 0x05h
      5. 7.6.5 Mode Register (Mode) Address - 0x06h
      6. 7.6.6 VCM Resonance Frequency Register (VCM_FREQ) Address - 0x07h
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VCM Mechanical Ringing Frequency
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 User Example 1
        2. 8.2.2.2 User Example 2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The VBAT pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of at least 1-µF rated for a minimum of 6.3 V. Place this capacitor as close to the VBAT and GND pins as possible with a thick trace or ground plane connection to the device GND pin.

10.2 Layout Example

DRV201A layout_ex_slvsb25.gifFigure 20. Recommended Layout Example