SLVSFY8B February   2020  – August 2021 DRV8210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics DSG Package
    7. 7.7 Typical Characteristics DRL Package
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Control Modes
        1. 8.3.2.1 PWM Control Mode (DSG: MODE = 0 and DRL)
        2. 8.3.2.2 PH/EN Control Mode (DSG: MODE = 1)
        3. 8.3.2.3 Half-Bridge Control Mode (DSG: MODE = Hi-Z)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 OUTx Overcurrent Protection (OCP)
        3. 8.3.3.3 Thermal Shutdown (TSD)
      4. 8.3.4 Pin Diagrams
        1. 8.3.4.1 Logic-Level Inputs
        2. 8.3.4.2 Tri-Level Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Sleep Mode
      3. 8.4.3 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Full-Bridge Driving
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Supply Voltage
          2. 9.2.1.2.2 Control Interface
          3. 9.2.1.2.3 Low-Power Operation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Half-Bridge Driving
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Supply Voltage
          2. 9.2.2.2.2 Control Interface
          3. 9.2.2.2.3 Low-Power Operation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Coil Relay Driving
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Supply Voltage
          2. 9.2.3.2.2 Control Interface
          3. 9.2.3.2.3 Low-Power Operation
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Current Sense
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Shunt Resistor Sizing
          2. 9.2.4.2.2 RC Filter
    3. 9.3 Current Capability and Thermal Performance
      1. 9.3.1 Power Dissipation and Output Current Capability
      2. 9.3.2 Thermal Performance
        1. 9.3.2.1 Steady-State Thermal Performance
        2. 9.3.2.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Low-Power Sleep Mode

The DRV8210 supports a low-power sleep mode to reduce current consumption from VM and VCC when the driver is not active. There are two ways to enter low-power sleep mode: autosleep and using the VCC pin. In autosleep mode, the device draws minimal current denoted by IVCCQ and IVMQ. Both DSG and DRL packages support autosleep. In VCC sleep mode, the device draws minimal current denoted by IVMQ_UV and IVCCQ_UV. Only the DSG package can go into low-power mode using the VCC pin. Table 8-7 describes how to enter low-power sleep mode.

Table 8-7 Sleep mode summary
Variant Input pin state OUT1 OUT2 Description
DRL IN1 = IN2 = 0 Hi-Z Hi-Z Autosleep for PWM or half-bridge interface: Upon entering this state, the outputs are disabled. The device remains in Active Mode for tSLEEP, then goes into low-power mode.
DSG MODE = 0, IN1 = IN2 = 0 Hi-Z Hi-Z
MODE = 1, EN = 0 L → Hi-Z L → Hi-Z Autosleep for PH/EN interface: Upon entering this state, both outputs go into brake mode by turning the low-side FETs on. The device remains in this state for tSLEEP, then goes into low-power mode. Once in low-power mode, the outputs are disabled.
VCC = 0 V Hi-Z Hi-Z VCC supply as sleep pin: The VCC pin can be supplied from a GPIO pin and used to put the device to sleep. By bringing the GPIO pin low, the device enters low-power mode by using UVLO. To wake up the device, set the GPIO pin high (VCC > VUVLO), then set EN = 1 if MODE = 1, or set/toggle either INx input to 1 if MODE = Hi-Z or 1. See Section 9.2.2.2.3 for more information on using the VCC pin for sleep.

The device returns to active mode when the input pins move to a state other than the ones in Table 8-7. To wake up the device from autosleep mode, the INx pins or EN pin (depending on MODE state) must be asserted high for longer than tWAKE before receiving PWM input signals.

To wake up the device from VCC sleep mode, the VCC pin voltage must be greater than VUVLO,VCC. Once the VCC pin has a valid voltage, either or both INx pins must be asserted high for longer than tWAKE to fully wake up the device. To protect the microcontroller GPIO pin from excess current due to the decoupling capacitor charging current, a resistor may need to be added between the GPIO and the decoupling capacitor on the VCC pin. See Section 9.2.2.2.3 for more information on designing this limiting resistor.

To ensure lowest supply current draw, TI recommends setting all input pins to logic low to eliminate current draw through the pulldown resistors in sleep mode. If the MODE pin is set to Hi-Z or logic low, it will not draw current in sleep mode. However, the MODE pin will draw some current in sleep mode when it is logic high.