SLVSA11G October 2009 – November 2015 DRV8828
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- PWP|28
Thermal pad, mechanical data (Package|Pins)
- PWP|28
Orderable Information
7 Detailed Description
7.1 Overview
The DRV8828 is an integrated motor driver solution for printers, scanners, and other automated equipment applications. The device integrates a single NMOS H-bridge, charge pump, current sense, current regulation, and device protection circuitry. The DRV8828 can be powered from a single voltage supply between 8.2 and 45 V and is capable of providing a continuous output current up to 3 A.
A simple PHASE/ENBL interface allows for easy interfacing to an external controller. A 5 bit current control scheme allows for up to 32 discrete current levels. The current regulation method is adjustable between slow, mixed, and fast decay.
Integrated protection circuits allows the device to monitor and protect against overcurrent, undervoltage, and overtemperature faults which are all reported through a fault indication pin (nFAULT). A low power sleep mode is integrated which allows the system to lower power consumption when not driving the motor.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 PWM Motor Drivers
The DRV8828 contains one H-bridge motor driver with current-control PWM circuitry. A block diagram of the motor control circuitry is shown in Figure 5. A bipolar stepper motor is shown, but the driver can also drive a DC motor.
Figure 5. Motor Control Circuitry
Note that there are multiple VM, ISEN, OUT, and VREF pins. All like-named pins must be connected together on the PCB.
7.3.2 Bridge Control
The PHASE input pin controls the direction of current flow through the H-bridge. The ENBL input pin enables the H-bridge outputs when active high. The logic inputs ENBL and PHASE have internal pulldown resistors of 100 kΩ. Table 1 shows the logic.
Table 1. H-Bridge Logic
| ENBL | PHASE | OUT1 | OUT2 |
|---|---|---|---|
| 0 | X | Z | Z |
| 1 | 1 | H | L |
| 1 | 0 | L | H |
7.3.3 Current Regulation
The current through the motor winding is regulated by a fixed-frequency PWM current regulation, or current chopping. When the H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and changing the current can be used to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the motor.
The PWM chopping current in the bridge is set by a comparator which compares the voltage across a current sense resistor connected to the ISEN pin, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the xVREF pins, and is scaled by a 5-bit DAC that allows current settings of zero to 100% in an approximately sinusoidal sequence.
The full-scale (100%) chopping current is calculated in Equation 1.
Example:
| If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be 3.3 V / (5 x 0.5 Ω) = 1.32 A. | ||
Five input pins (I0 - I4) are used to scale the current in the bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The logic inputs I0, I1, I2, I3 and I4 have internal pulldown resistors of 100 kΩ. The function of the pins is shown in Table 2.
Table 2. H-Bridge Pin Functions
| I[4..0] | RELATIVE CURRENT (% FULL-SCALE CHOPPING CURRENT) |
|---|---|
| 0x00h | 0% |
| 0x01h | 5% |
| 0x02h | 10% |
| 0x03h | 15% |
| 0x04h | 20% |
| 0x05h | 24% |
| 0x06h | 29% |
| 0x07h | 34% |
| 0x08h | 38% |
| 0x09h | 43% |
| 0x0Ah | 47% |
| 0x0Bh | 51% |
| 0x0Ch | 56% |
| 0x0Dh | 60% |
| 0x0Eh | 63% |
| 0x0Fh | 67% |
| 0x10h | 71% |
| 0x11h | 74% |
| 0x12h | 77% |
| 0x13h | 80% |
| 0x14h | 83% |
| 0x15h | 86% |
| 0x16h | 88% |
| 0x17h | 90% |
| 0x18h | 92% |
| 0x19h | 94% |
| 0x1Ah | 96% |
| 0x1Bh | 97% |
| 0x1Ch | 98% |
| 0x1Dh | 99% |
| 0x1Eh | 100% |
| 0x1Fh | 100% |
7.3.4 Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown indicates the state when the PHASE pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 6 as case 3.
Figure 6. Decay Mode
The DRV8828 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of approximately 130 kÙ and an internal pulldown resistor of approximately 80 kÙ. This sets the mixed decay mode if the pin is left open or undriven.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period.
7.3.5 Blanking Time
After the current is enabled in the H-bridge, the voltage on the ISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 µs. Note that the blanking time also sets the minimum on time of the PWM.
7.3.6 Protection Circuits
The DRV8828 is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
7.3.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
7.3.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold.
7.4 Device Functional Modes
7.4.1 nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs are ignored while nRESET is active. The nRESET pin has an internal pulldown resistor of 100 kΩ. The nSLEEP pin has an internal pulldown resistor of 1 MΩ.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridge is disabled, the gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational.