SLVSEE9D April   2020  – April 2021 DRV8889-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 rms Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mode 4: Slow Decay for Increasing Current, Fast Decay for Decreasing current
        4. 7.3.6.4 Mixed Decay for Increasing and Decreasing Current
        5. 7.3.6.5 Smart tune Dynamic Decay
        6. 7.3.6.6 Smart tune Ripple Control
      7. 7.3.7  Blanking Time
      8. 7.3.8  Charge Pump
      9. 7.3.9  Linear Voltage Regulators
      10. 7.3.10 Logic Level Pin Diagrams
        1. 7.3.10.1 nFAULT Pin
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 Latched Shutdown (OCP_MODE = 0b)
          2. 7.3.11.3.2 Automatic Retry (OCP_MODE = 1b)
        4. 7.3.11.4 Open-Load Detection (OL)
        5. 7.3.11.5 Stall Detection
        6. 7.3.11.6 Thermal Shutdown (OTSD)
          1. 7.3.11.6.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 7.3.11.6.2 Automatic Recovery (OTSD_MODE = 1b)
        7. 7.3.11.7 Overtemperature Warning (OTW)
        8. 7.3.11.8 Undertemperature Warning (UTW)
        9.       53
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, DRVOFF = 1)
      3. 7.4.3 Operating Mode (nSLEEP = 1, DRVOFF = 0)
      4. 7.4.4 nSLEEP Reset Pulse
      5.      59
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
          1. 8.2.4.1.1 Conduction Loss
          2. 8.2.4.1.2 Switching Loss
          3. 8.2.4.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.4.1.4 Total Power Dissipation
        2. 8.2.4.2 PCB Types
        3. 8.2.4.3 Thermal Parameters for HTSSOP Package
        4. 8.2.4.4 Thermal Parameters for VQFN Package
        5. 8.2.4.5 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Register Maps

Table 7-16 lists the memory-mapped registers for the DRV8889-Q1 device. All register addresses not listed in Table 7-16 should be considered as reserved locations and the register contents should not be modified.

Table 7-16 lists the memory-mapped registers for the DRV8889A-Q1 device. All register addresses not listed in Table 7-16 should be considered as reserved locations and the register contents should not be modified.

Table 7-16 Memory Map
Register
Name		 7 6 5 4 3 2 1 0 Access
Type		 Address
FAULT Status FAULT SPI_ERROR UVLO CPUV OCP STL TF OL R 0x00
DIAG Status 1 OCP_LS2_B OCP_HS2_B OCP_LS1_B OCP_HS1_B OCP_LS2_A OCP_HS2_A OCP_LS1_A OCP_HS1_A R 0x01
DIAG Status 2 UTW OTW OTS STL_LRN_OK STALL RSVD OL_B OL_A R 0x02
CTRL1 TRQ_DAC [3:0] RSVD SLEW_RATE [1:0] RW 0x03
CTRL2 DIS_OUT RSVD TOFF [1:0] DECAY [2:0] RW 0x04
CTRL3 DIR STEP SPI_DIR SPI_STEP MICROSTEP_MODE [3:0] RW 0x05
CTRL4 CLR_FLT LOCK [2:0] EN_OL OCP_MODE OTSD_MODE TW_REP RW 0x06
CTRL5 RSVD STL_LRN EN_STL STL_REP RSVD RW 0x07
CTRL6 STALL_TH [7:0] RW 0x08
CTRL7 TRQ_COUNT [7:0] R 0x09
CTRL8 RSVD REV_ID [3:0] R 0x0A
Table 7-17 Memory Map
Register
Name		 7 6 5 4 3 2 1 0 Access
Type		 Address
FAULT Status FAULT SPI_ERROR UVLO CPUV OCP STL TF OL R 0x00
DIAG Status 1 OCP_LS2_B OCP_HS2_B OCP_LS1_B OCP_HS1_B OCP_LS2_A OCP_HS2_A OCP_LS1_A OCP_HS1_A R 0x01
DIAG Status 2 UTW OTW OTS STL_LRN_OK STALL RSVD OL_B OL_A R 0x02
CTRL1 TRQ_DAC [3:0] RSVD SLEW_RATE [1:0] RW 0x03
CTRL2 DIS_OUT RSVD TOFF [1:0] DECAY [2:0] RW 0x04
CTRL3 DIR STEP SPI_DIR SPI_STEP MICROSTEP_MODE [3:0] RW 0x05
CTRL4 CLR_FLT LOCK [2:0] EN_OL OCP_MODE OTSD_MODE TW_REP RW 0x06
CTRL5 RSVD STL_LRN EN_STL STL_REP OL_TIME [1:0] EN_SR_BLANK RW 0x07
CTRL6 STALL_TH [7:0] RW 0x08
CTRL7 TRQ_COUNT [7:0] R 0x09
CTRL8 RSVD REV_ID [3:0] R 0x0A

The differences between the register maps of the DRV8889-Q1 and DRV8889A-Q1 are - DRV8889A-Q1 has OL_TIME [1:0] and EN_SR_BLANK bits in CTRL5 register to program open-load detection time and slow-decay to drive mode blanking time. Also, the default value of the DIS_OUT bit in CTRL2 register is different in DRV8889A-Q1.

Complex bit access types are encoded to fit into small table cells. Table 7-18 shows the codes that are used for access types in this section.

Table 7-18 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.6.1 Status Registers

The status registers are used to reporting warning and fault conditions. Status registers are read-only registers

Table 7-19 lists the memory-mapped registers for the status registers. All register offset addresses not listed in Table 7-19 should be considered as reserved locations and the register contents should not be modified.

Table 7-19 Status Registers Summary Table
AddressRegister NameSection
0x00FAULT statusGo
0x01DIAG status 1Go
0x02DIAG status 2Go

7.6.2 FAULT Status Register Name (address = 0x00)

FAULT status is shown in Figure 7-33 and described in Figure 7-33.

Read-only

Figure 7-33 FAULT Status Register
76543210
FAULTSPI_ERRORUVLOCPUVOCPSTLTFOL
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-20 FAULT Status Register Field Descriptions
BitFieldTypeDefaultDescription
7FAULTR0b

When nFAULT pin is at 1, FAULT bit is 0. When nFAULT pin is at 0, FAULT bit is 1.

6SPI_ERRORR0b

Indicates SPI protocol errors, such as more SCLK pulses than are required or SCLK is absent even though nSCS is low. Becomes high in fault and the nFAULT pin is driven low. Normal operation resumes when the protocol error is removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse.

5UVLOR0b

Indicates an undervoltage lockout fault condition.

4CPUVR0b

Indicates charge pump undervoltage fault condition.

3OCPR0b

Indicates overcurrent fault condition

2STLR0b

Indicates motor stall condition.

1TFR0b

Logic OR of the overtemperature warning, undertemperature warning and overtemperature shutdown.

0OLR0b

Indicates open-load condition.

7.6.3 DIAG Status 1 (address = 0x01)

DIAG Status 1 is shown in Figure 7-34 and described in Table 7-21.

Read-only

Figure 7-34 DIAG Status 1 Register
76543210
OCP_LS2_BOCP_HS2_BOCP_LS1_BOCP_HS1_BOCP_LS2_AOCP_HS2_AOCP_LS1_AOCP_HS1_A
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-21 DIAG Status 1 Register Field Descriptions
BitFieldTypeDefaultDescription
7OCP_LS2_BR0b

Indicates overcurrent fault on the low-side FET of half bridge 2 in BOUT

6OCP_HS2_BR0b

Indicates overcurrent fault on the high-side FET of half bridge 2 in BOUT

5OCP_LS1_BR0b

Indicates overcurrent fault on the low-side FET of half bridge 1 in BOUT

4OCP_HS1_BR0b

Indicates overcurrent fault on the high-side FET of half bridge 1 in BOUT

3OCP_LS2_AR0b

Indicates overcurrent fault on the low-side FET of half bridge 2 in AOUT

2OCP_HS2_AR0b

Indicates overcurrent fault on the high-side FET of half bridge 2 in AOUT

1OCP_LS1_AR0b

Indicates overcurrent fault on the low-side FET of half bridge 1 in AOUT

0OCP_HS1_AR0b

Indicates overcurrent fault on the high-side FET of half bridge 1 in AOUT

7.6.4 DIAG Status 2 (address = 0x02)

DIAG Status 2 is shown in Figure 7-35 and described in Table 7-22.

Read-only

Figure 7-35 DIAG Status 2 Register
76543210
UTWOTWOTSSTL_LRN_OKSTALLRSVDOL_BOL_A
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-22 DIAG Status 2 Register Field Descriptions
BitFieldTypeDefaultDescription
7UTWR0b

Indicates undertemperature warning.

6OTWR0b

Indicates overtemperature warning.

5OTSR0b

Indicates overtemperature shutdown.

4STL_LRN_OKR0b

Indicates stall detection learning is successful

3STALLR0b

Indicates motor stall condition

2RSVDR0b

Reserved.

1OL_BR0b

Indicates open-load detection on BOUT

0OL_AR0b

Indicates open-load detection on AOUT

7.6.5 Control Registers

The IC control registers are used to configure the device. Status registers are read and write capable.

Table 7-23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in Table 7-23 should be considered as reserved locations and the register contents should not be modified.

Table 7-23 Control Registers Summary Table
AddressRegister NameSection
0x03CTRL1Go
0x04CTRL2Go
0x05CTRL3Go
0x06CTRL4Go
0x07CTRL5Go
0x08CTRL6Go
0x09CTRL7Go

7.6.6 CTRL1 Control Register (address = 0x03)

CTRL1 control is shown in Figure 7-36 and described in Table 7-24.

Read/Write

Figure 7-36 CTRL1 Control Register
76543210
TRQ_DAC [3:0]RSVDSLEW_RATE [1:0]
R/W-0000bR/W-00bR/W-00b
Table 7-24 CTRL1 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-4TRQ_DAC [3:0]R/W0000b

0000b = 100%

0001b = 93.75%

0010b = 87.5%

0011b = 81.25%

0100b = 75%

0101b = 68.75%

0110b = 62.5%

0111b = 56.25%

1000b = 50%

1001b = 43.75%

1010b = 37.5%

1011b = 31.25%

1100b = 25%

1101b = 18.75%

1110b = 12.5%

1111b = 6.25%

3-2RSVDR/W00b

Reserved

1-0SLEW_RATE [1:0]R/W00b

00b = 10-V/µs

01b = 35-V/µs

10b = 50-V/µs

11b = 105-V/µs

7.6.7 CTRL2 Control Register (address = 0x04)

CTRL2 is shown in Figure 7-37 and CTRL2 Control Register for DRV8889A-Q1 and described in Table 7-25.

Read/Write

Figure 7-37 CTRL2 Control Register for DRV8889-Q1
76543210
DIS_OUTRSVDTOFF [1:0]DECAY [2:0]
R/W-0bR/W-00bR/W-01bR/W-111b
Table 7-25 CTRL2 Control Register Field Descriptions for DRV8889-Q1
BitFieldTypeDefaultDescription
7DIS_OUTR/W

0b (DRV8889-Q1)

1b (DRV8889A-Q1)

Write '1' to Hi-Z all outputs. Write '0' to enable all outputs. OR'ed with DRVOFF pin. To prevent false OL detection, ensure OL fault detection is disabled by writing '0' to EN_OL bit, before making the outputs Hi-Z by writing '1' to DIS_OUT.

6-5RSVDR/W00b

Reserved

4-3TOFF [1:0]R/W01b

00b = 7 µs

01b = 16 µs

10b = 24 µs

11b = 32 µs

2-0DECAY [2:0]R/W111b

000b = Increasing SLOW, decreasing SLOW

001b = Increasing SLOW, decreasing MIXED 30%

010b = Increasing SLOW, decreasing MIXED 60%

011b = Increasing SLOW, decreasing FAST

100b = Increasing MIXED 30%, decreasing MIXED 30%

101b = Increasing MIXED 60%, decreasing MIXED 60%

110b = Smart tune Dynamic Decay

111b = Smart tune Ripple Control

7.6.8 CTRL3 Control Register (address = 0x05)

CTRL3 is shown in Figure 7-38 and described in Table 7-26.

Read/Write

Figure 7-38 CTRL3 Control Register
76543210
DIRSTEPSPI_DIRSPI_STEPMICROSTEP_MODE [3:0]
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0000b
Table 7-26 CTRL3 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7DIRR/W0b

Direction input. Logic '1' sets the direction of stepping, when SPI_DIR = 1.

6STEPR/W0b

Step input. Logic '1' causes the indexer to advance one step, when SPI_STEP = 1. This bit is self-clearing, automatically becomes '0' after writing '1'.

5SPI_DIRR/W0b

0b = Outputs follow input pin for DIR

1b = Outputs follow SPI registers DIR

4SPI_STEPR/W0b

0b = Outputs follow input pin for STEP

1b = Outputs follow SPI registers STEP

3-0MICROSTEP_MODE [3:0]R/W0000b

0000b = Full step (2-phase excitation) with 100% current

0001b = Full step (2-phase excitation) with 71% current

0010b = Non-circular 1/2 step

0011b = 1/2 step

0100b = 1/4 step

0101b = 1/8 step

0110b = 1/16 step

0111b = 1/32 step

1000b = 1/64 step

1001b = 1/128 step

1010b = 1/256 step

1011b to 1111b = Reserved

7.6.9 CTRL4 Control Register (address = 0x06)

CTRL4 is shown in Figure 7-39 and described in Table 7-27.

Read/Write

Figure 7-39 CTRL4 Control Register
76543210
CLR_FLTLOCK [2:0]EN_OLOCP_MODEOTSD_MODETW_REP
R/W-0bR/W-011bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-27 CTRL4 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7CLR_FLTR/W0b

Write '1' to this bit to clear all latched fault bits. This bit automatically resets after being written.

6-4LOCK [2:0]R/W011b

Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x06h bit 7 (CLR_FLT). Writing any sequence other than 110b has no effect when unlocked.

Write 011b to this register to unlock all registers. Writing any sequence other than 011b has no effect when locked.

3EN_OLR/W0b

Write '1' to enable open load detection

2OCP_MODER/W0b

0b = Overcurrent condition causes a latched fault

1b = Overcurrent condition causes an automatic retrying fault

1OTSD_MODER/W0b

0b = Overtemperature condition will cause latched fault

1b = Overtemperature condition will cause automatic recovery fault

0TW_REPR/W0b

0b = Overtemperature or undertemperature warning is not reported on the nFAULT line

1b = Overtemperature or undertemperature warning is reported on the nFAULT line

7.6.10 CTRL5 Control Register (address = 0x07)

CTRL5 for DRV8889A-Q1 is shown in Figure 7-40 and described in Table 7-28.

CTRL5 for DRV8889-Q1 is shown in Figure 7-41 and described in Table 7-29.

DRV8889A-Q1 features programable open-load detection time using the OL_TIME [1:0] bits and programmable slow-decay to drive blanking time using the EN_SR_BLANK bit.

Read/Write

Figure 7-40 CTRL5 Control Register for DRV8889A-Q1
76543210
RSVDSTL_LRNEN_STLSTL_REPOL_TIME [1:0]EN_SR_BLANK
R/W-00bR/W-0bR/W-0bR/W-1bR/W-00bR/W-0b
Figure 7-41 CTRL5 Control Register for DRV8889-Q1
76543210
RSVDSTL_LRNEN_STLSTL_REPRSVD
R/W-00bR/W-0bR/W-0bR/W-1bR/W-000b
Table 7-28 CTRL5 Control Register Field Descriptions for DRV8889A-Q1
BitFieldTypeDefaultDescription
7-6RSVDR/W00b

Reserved. Should always be '00'.

5STL_LRNR/W0b

Write '1' to learn stall count for stall detection. This bit automatically returns to '0' when the stall learning process is complete.

4EN_STLR/W0b

0b = Stall detection is disabled

1b = Stall detection is enabled

3STL_REPR/W1b

0b = Stall detection is not reported on nFAULT

1b = Stall detection is reported on nFAULT

2-1OL_TIME [1:0]R/W00b

00b = 200ms (max.) open load detection time

01b = 125ms (max.) open load detection time

10b = 75ms (max.) open load detection time

11b = 3ms (max.) open load detection time

0EN_SR_BLANKR/W0b

0b = 500ns slow-decay to drive blanking time

1b = slow-decay to drive blanking will depend on slew rate, shown in Table 7-9.

Table 7-29 CTRL5 Control Register Field Descriptions for DRV8889-Q1
BitFieldTypeDefaultDescription
7-6RSVDR/W00b

Reserved. Should always be '00'.

5STL_LRNR/W0b

Write '1' to learn stall count for stall detection. This bit automatically returns to '0' when the stall learning process is complete.

4EN_STLR/W0b

0b = Stall detection is disabled

1b = Stall detection is enabled

3STL_REPR/W1b

0b = Stall detection i s not reported on nFAULT

1b = Stall detection is reported on nFAULT

2-0RSVDR/W000b

Reserved. Should always be '000'.

7.6.11 CTRL6 Control Register (address = 0x08)

CTRL6 is shown in Figure 7-42 and described in Table 7-30.

Read/Write

Figure 7-42 CTRL6 Control Register
76543210
STALL_TH [7:0]
R/W-00001111b
Table 7-30 CTRL6 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-0STALL_TH [7:0]R/W00001111b

00000000b = 0 count

XXXXXXXXb = 1 to 254 counts

11111111b = 255 counts

7.6.12 CTRL7 Control Register (address = 0x09)

CTRL7 is shown in Figure 7-43 and described in Table 7-31.

Read-only

Figure 7-43 CTRL7 Control Register
76543210
TRQ_COUNT [7:0]
R-11111111b
Table 7-31 CTRL7 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-0TRQ_COUNT [7:0]R11111111b

00000000b = 0 count

XXXXXXXXb = 1 to 254 counts

11111111b = 255 counts

7.6.13 CTRL8 Control Register (address = 0x0A)

CTRL8 is shown in Figure 7-44 and described in Table 7-32.

Read-only

Figure 7-44 CTRL8 Control Register
76543210
RSVDREV_ID [3:0]
R-0000bR-0010b
Table 7-32 CTRL8 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-4RSVDR0000b

Reserved

3-0REV_IDR0010b

Silicon Revision Identification.

0000b indicates 1st Prototype Revision.

0001b indicates 2nd Prototype Revision.

0010b indicates Production Revision.