SNLS624 September   2018 DSLVDS1048

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Feature
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Probing LVDS Transmission Lines
        2. 9.2.2.2 Threshold
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Decoupling Recommendations
      2. 11.1.2 Differential Traces
      3. 11.1.3 Termination
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DSLVDS1048 TSSOP (16) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.