SNOSCZ5A June   2015  – June 2015 FDC2112 , FDC2114 , FDC2212 , FDC2214

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics - I2C
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Clocking Architecture
      2. 9.3.2 Multi-Channel and Single-Channel Operation
        1. 9.3.2.1 Gain and Offset (FDC2112, FDC2114 only)
      3. 9.3.3 Current Drive Control Registers
      4. 9.3.4 Device Status Registers
      5. 9.3.5 Input Deglitch Filter
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-up Mode
      2. 9.4.2 Normal (Conversion) Mode
      3. 9.4.3 Sleep Mode
      4. 9.4.4 Shutdown Mode
        1. 9.4.4.1 Reset
    5. 9.5 Programming
      1. 9.5.1 I2C Interface Specifications
    6. 9.6 Register Maps
      1. 9.6.1  Register List
      2. 9.6.2  Address 0x00, DATA_CH0
      3. 9.6.3  Address 0x01, DATA_LSB_CH0 (FDC2212 / FDC2214 only)
      4. 9.6.4  Address 0x02, DATA_CH1
      5. 9.6.5  Address 0x03, DATA_LSB_CH1 (FDC2212 / FDC2214 only)
      6. 9.6.6  Address 0x04, DATA_CH2 (FDC2114, FDC2214 only)
      7. 9.6.7  Address 0x05, DATA_LSB_CH2 (FDC2214 only)
      8. 9.6.8  Address 0x06, DATA_CH3 (FDC2114, FDC2214 only)
      9. 9.6.9  Address 0x07, DATA_LSB_CH3 (FDC2214 only)
      10. 9.6.10 Address 0x08, RCOUNT_CH0
      11. 9.6.11 Address 0x09, RCOUNT_CH1
      12. 9.6.12 Address 0x0A, RCOUNT_CH2 (FDC2114, FDC2214 only)
      13. 9.6.13 Address 0x0B, RCOUNT_CH3 (FDC2114, FDC2214 only)
      14. 9.6.14 Address 0x0C, OFFSET_CH0 (FDC21112 / FDC2114 only)
      15. 9.6.15 Address 0x0D, OFFSET_CH1 (FDC21112 / FDC2114 only)
      16. 9.6.16 Address 0x0E, OFFSET_CH2 (FDC2114 only)
      17. 9.6.17 Address 0x0F, OFFSET_CH3 (FDC2114 only)
      18. 9.6.18 Address 0x10, SETTLECOUNT_CH0
      19. 9.6.19 Address 0x11, SETTLECOUNT_CH1
      20. 9.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114, FDC2214 only)
      21. 9.6.21 Address 0x13, SETTLECOUNT_CH3 (FDC2114, FDC2214 only)
      22. 9.6.22 Address 0x14, CLOCK_DIVIDERS_CH0
      23. 9.6.23 Address 0x15, CLOCK_DIVIDERS_CH1
      24. 9.6.24 Address 0x16, CLOCK_DIVIDERS_CH2 (FDC2114, FDC2214 only)
      25. 9.6.25 Address 0x17, CLOCK_DIVIDERS_CH3 (FDC2114, FDC2214 only)
      26. 9.6.26 Address 0x18, STATUS
      27. 9.6.27 Address 0x19, ERROR_CONFIG
      28. 9.6.28 Address 0x1A, CONFIG
      29. 9.6.29 Address 0x1B, MUX_CONFIG
      30. 9.6.30 Address 0x1C, RESET_DEV
      31. 9.6.31 Address 0x1E, DRIVE_CURRENT_CH0
      32. 9.6.32 Address 0x1F, DRIVE_CURRENT_CH1
      33. 9.6.33 Address 0x20, DRIVE_CURRENT_CH2 (FDC2114 / FDC2214 only)
      34. 9.6.34 Address 0x21, DRIVE_CURRENT_CH3 (FDC2114 / FDC2214 only)
      35. 9.6.35 Address 0x7E, MANUFACTURER_ID
      36. 9.6.36 Address 0x7F, DEVICE_ID
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Sensor Configuration
      2. 10.1.2 Shield
    2. 10.2 Typical Application
      1. 10.2.1 Schematic
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Application Performance Plot
        2. 10.2.3.2 Recommended Initial Register Configuration Values
        3. 10.2.3.3 Inductor Self-Resonant Frequency
      4. 10.2.4 Application Curves
      5. 10.2.5 Power-Cycled Applications
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

(1)
MIN MAX UNIT
VDD Supply voltage range 5 V
Vi Voltage on any pin –0.3 VDD + 0.3 V
IA Input current on any INx pin –8 8 mA
ID Input current on any digital pin –5 5 mA
TJ Junction temperature –55 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
FDC2112 / FDC2212 in 12-pin WSON package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
FDC2114 / FDC2214 in 16-pin WQFN package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
MIN NOM MAX UNIT
VDD Supply voltage 2.7 3.6 V
TA Operating temperature –40 125 °C

8.4 Thermal Information

THERMAL METRIC(1) FDC2112 / FDC2212 FDC2214 / FDC2214 UNIT
DNT (WSON) RGH (WQFN)
12 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 50 38 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V(1)
PARAMETER TEST CONDITIONS(2) MIN(3) TYP(4) MAX(3) UNIT
POWER
VDD Supply voltage TA = –40°C to +125°C 2.7 3.6 V
IDD Supply durrent (not including sensor current)(5) CLKIN = 10MHz(6) 2.1 mA
IDDSL Sleep mode supply current(5) 35 60 µA
ISD Shutdown mode supply current(5) 0.2 1 µA
CAPACITIVE SENSOR
CSENSORMAX Maximum sensor capacitance 1mH inductor, 10kHz oscillation 250 nF
CIN Sensor pin parasitic capacitance 4 pF
NBITS Number of bits FDC2112, FDC2114
RCOUNT ≥ 0x0400		 12 bits
FDC2212, FDC2214
RCOUNT = 0xFFFF		 28 bits
fCS Maximum channel sample rate FDC2112, FDC2114
single active channel continuous conversion, SCL = 400 kHz		 13.3 kSPS
FDC2212, FDC2214
single active channel continuous conversion, SCL= 400 kHz		 4.08 kSPS
EXCITATION
fSENSOR Sensor excitation frequency TA = –40°C to +125°C 0.01 10 MHz
VSENSORMIN Minimum sensor oscillation amplitude (pk)(7) 1.2 V
VSENSORMAX Maximum sensor oscillation amplitude (pk) 1.8 V
ISENSORMAX Sensor maximum current drive HIGH_CURRENT_DRV = b0
DRIVE_CURRENT_CH0 = 0xF800		 1.5 mA
HIGH_CURRENT_DRV = b1
DRIVE_CURRENT_CH0 = 0xF800
Channel 0 only		 6 mA
MASTER CLOCK
fCLKIN External master clock input frequency (CLKIN) TA = –40°C to +125°C 2 40 MHz
CLKINDUTY_MIN External master clock minimum acceptable duty cycle (CLKIN) 40%
CLKINDUTY_MAX External master clock maximum acceptable duty cycle (CLKIN) 60%
VCLKIN_LO CLKIN low voltage threshold 0.3*VDD V
VCLKIN_HI CLKIN high voltage threshold 0.7*VDD V
fINTCLK Internal master clock frequency range 35 43.4 55 MHz
TCf_int_μ Internal master clock temperature coefficient mean –13 ppm/°C
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Register values are represented as either binary (b is the prefix to the digits), or hexadecimal (0x is the prefix to the digits). Decimal values have no prefix.
(3) Limits are ensured by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(5) I2C read/write communication and pull-up resistors current through SCL, SDA not included.
(6) Sensor capacitor: 1 layer, 20.9 x 13.9 mm, Bourns CMH322522-180KL sensor inductor with L=18µH and 33pF 1% COG/NP0 Target: Grounded aluminum plate (176 x 123 mm), Channel = Channel 0 (continuous mode) CLKIN = 40 MHz, CHx_FIN_SEL = b10, CHx_FREF_DIVIDER = b00 0000 0001 CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100, DRIVE_CURRENT_CH0 = 0x7800.
(7) Lower VSENSORMIN oscillation amplitudes can be used, but will result in lower SNR.

8.6 Timing Requirements

MIN NOM MAX UNIT
tSDWAKEUP Wake-up time from SD high-low transition to I2C readback 2 ms
tSLEEPWAKEUP Wake-up time from sleep mode 0.05 ms
tWD-TIMEOUT Sensor recovery time (after watchdog timeout) 5.2 ms
I2C TIMING CHARACTERISTICS
fSCL Clock frequency 10 400 kHz
tLOW Clock low time 1.3 μs
tHIGH Clock high time 0.6 μs
tHD;STA Hold time (repeated) START condition: after this period, the first clock pulse is generated 0.6 μs
tSU;STA Setup time for a repeated START condition 0.6 μs
tHD;DAT Data hold time 0 μs
tSU;DAT Data setup time 100 ns
tSU;STO Setup time for STOP condition 0.6 μs
tBUF Bus free time between a STOP and START condition 1.3 μs
tVD;DAT Data valid time 0.9 μs
tVD;ACK Data valid acknowledge time 0.9 μs
tSP Pulse width of spikes that must be suppressed by the input filter(1) 50 ns
FDC2212 FDC2214 FDC2112 FDC2114 td_I2C_timing_snoscy9.gifFigure 1. I2C Timing

8.7 Switching Characteristics - I2C

Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE LEVELS
VIH Input high voltage 0.7ˣVDD V
VIL Input low voltage 0.3ˣVDD V
VOL Output low voltage (3 mA sink current) 0.4 V
HYS Hysteresis 0.1ˣVDD V
(1) This parameter is specified by design and/or characterization and is not tested in production.

8.8 Typical Characteristics

Common test conditions (unless specified otherwise): Sensor capacitor: 1 layer, 20.9 x 13.9 mm, Bourns CMH322522-180KL sensor inductor with L=18 µH and 33 pF 1% COG/NP0 Target: Grounded aluminum plate (176 x 123 mm), Channel = Channel 0 (continuous mode) CLKIN = 40 MHz, CHx_FIN_SEL = b01, CHx_FREF_DIVIDER = b00 0000 0001 CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100, DRIVE_CURRENT_CH0 = 0x7800.
FDC2212 FDC2214 FDC2112 FDC2114 D003_SNOSCY9.gif
Includes 1.57 mA sensor current
–40°C to +125°C
Figure 2. Active Mode IDD vs. Temperature
FDC2212 FDC2214 FDC2112 FDC2114 D005_SNOSCY9.gif
–40°C to +125°C
Figure 4. Sleep Mode IDD vs. Temperature
FDC2212 FDC2214 FDC2112 FDC2114 D007_SNOSCY9.gif
–40°C to +125°C
Figure 6. Shutdown Mode IDD vs. Temperature
FDC2212 FDC2214 FDC2112 FDC2114 D009_SNOSCY9.gif
–40°C to +125°C
Figure 8. Internal Oscillator Frequency vs. Temperature
FDC2212 FDC2214 FDC2112 FDC2114 D004_SNOSCY9.gif
Includes 1.57 mA sensor current
Figure 3. Active Mode IDD vs. VDD
FDC2212 FDC2214 FDC2112 FDC2114 D006_SNOSCY9.gif
Figure 5. Sleep Mode IDD vs. VDD
FDC2212 FDC2214 FDC2112 FDC2114 D008_SNOSCY9.gif
Figure 7. Shutdown Mode IDD vs. VDD
FDC2212 FDC2214 FDC2112 FDC2114 D010_SNOSCY9.gif
Data based on 1 unit
Figure 9. Internal Oscillator Frequency vs. VDD