SLLSES1D December   2015  – September 2020 HD3SS3220

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Device
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DFP/Source – Downstream Facing Port
      2. 7.3.2  UFP/Sink – Upstream Facing Port
      3. 7.3.3  DRP – Dual Role Port
      4. 7.3.4  Cable Orientation and Mux Control
      5. 7.3.5  Type-C Current Mode
      6. 7.3.6  Accessory Support
      7. 7.3.7  Audio Accessory
      8. 7.3.8  Debug Accessory
      9. 7.3.9  VCONN support for Active Cables
      10. 7.3.10 I2C and GPIO Control
      11. 7.3.11 HD3SS3220 V(BUS) Detection
      12. 7.3.12 VDD5 and VCC33 Power-On Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Dead Battery
      4. 7.4.4 Shutdown Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
      2. 7.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]
      3. 7.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
      4. 7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
      5. 7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application, DRP Port
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application, DFP Port
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Typical Application, UFP Port
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Suggested PCB Stackups
      2. 9.1.2 High-Speed Signal Trace Length Matching
      3. 9.1.3 Differential Signal Spacing
      4. 9.1.4 High-Speed Differential Signal Rules
      5. 9.1.5 Symmetry in the Differential Pairs
      6. 9.1.6 Via Discontinuity Mitigation
      7. 9.1.7 Surface-Mount Device Pad Discontinuity Mitigation
      8. 9.1.8 ESD/EMI Considerations
    2. 9.2 Layout
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Programming

For further programmability, the HD3SS3220 can be controlled using I2C. The HD3SS3220 local I2C interface is available for reading/writing after x clock cycles when the device is powered up. The SCL and SDA terminals are used for I2C clock and I2C data respectively. If I2C is the preferred method of control, the ADDR pin must be set accordingly.

Table 7-5 HD3SS3220 I2C Target Address
ADDR pinBit 7 (MSB)Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 (W/R)
H11001110/1
L10001110/1

The following procedure should be followed to write to HD3SS3220 I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the HD3SS3220 7-bit address and a zero-value R/W bit to indicate a write cycle.
  2. The HD3SS3220 device acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within the HD3SS3220 device) to be written, consisting of one byte of data, MSB-first.
  4. The HD3SS3220 device acknowledges the sub-address cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The HD3SS3220 device acknowledges the byte transfer.
  7. The master can continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the HD3SS3220 device.
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the HD3SS3220 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the HD3SS3220 7-bit address and a one-value R/W bit to indicate a read cycle.
  2. The HD3SS3220 device acknowledges the address cycle.
  3. The HD3SS3220 device transmits the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the I2C register occurred prior to the read, then the HD3SS3220 device starts at the sub-address specified in the write.
  4. The HD3SS3220 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the HD3SS3220 device transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the HD3SS3220 7-bit address and a zero-value R/W bit to indicate a read cycle.
  2. The HD3SS3220 device acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within the HD3SS3220 device) to be read, consisting of one byte of data, MSB-first.
  4. The HD3SS3220 device acknowledges the sub-address cycle.
  5. The master terminates the read operation by generating a stop condition (P).

Note:

If no sub-addressing is included for the read procedure, then the reads start at register offset 00h and continue byte-by-byte through the registers until the I2C master terminates the read operation. If a I2C address write occurred prior to the read, then the reads start at the sub-address specified by the address write.