SBOS464B september   2019  – june 2023 INA333-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Offset Correction
      2. 7.3.2 Input Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Common-Mode Range
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Gain
        2. 8.2.2.2 Offset Trimming
        3. 8.2.2.3 Noise Performance
        4. 8.2.2.4 Input Bias Current Return Path
        5. 8.2.2.5 Low Voltage Operation
        6. 8.2.2.6 Single-Supply Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 TINA-TI Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT(1)
VOSI Input stage offset voltage(2) ±10 ±25 μV
vs temperature, TA = –40°C to +125°C ±0.1 μV/°C
VOSO Output stage offset voltage(2) ±25 ±110 μV
vs temperature, TA = –40°C to +125°C ±0.5 μV/°C
PSRR Power-supply rejection ratio 90 102 dB
Zid Differential impedance 100 || 3 GΩ || pF
Zic Common-mode impedance 100 || 3 GΩ || pF
VCM Common-mode voltage VO = 0 V (V–) + 0.1 (V+) – 0.1 V
CMRR Common-mode rejection ratio DC to 60 Hz, 
VS = 5.5 V, VCM = (V–) + 0.1 V to (V+) – 0.1 V		 G = 1 78 90 dB
G = 10 96 110
G = 100 96 115
G = 1000 96 115
INPUT BIAS CURRENT
IB Input bias current ±70 ±280 pA
TA = –40°C to +125°C See Figure 6-26 pA/°C
IOS Input offset current ±50 ±280 pA
TA = –40°C to +125°C See Figure 6-28 pA/°C
INPUT VOLTAGE NOISE
eNI Input voltage noise G = 100, RS = 0 Ω f = 10 Hz 50 nV/√Hz
f = 100 Hz 50
f = 1 kHz 50
f = 0.1 Hz to 10 Hz 1 μVPP
In Input current noise f = 10 Hz 100 fA/√Hz
f = 0.1 Hz to 10 Hz 2 pAPP
GAIN
Gain equation 1 + (100 kΩ / RG) V/V
G Gain 1 1000 V/V
GE Gain error VS = 5.5 V,
(V–) + 100 mV ≤ VO ≤ (V+) – 100 mV		 G = 1 ±0.01 ±0.1 %

G = 10		 ±0.05 ±0.25

G = 100		 ±0.07 ±0.25

G = 1000		 ±0.25 ±0.5
Gain vs temperature TA = –40°C to +125°C ±1 ±5 ppm/°C
G > 1(3) ±15 ±50
Gain nonlinearity G = 1 to 1000
VS = 5.5 V, (V–) + 100 mV ≤ VO ≤ (V+) – 100 mV		 10 ppm
OUTPUT
Output voltage swing from rail VS = 5.5 V 40 50 mV
Capacitive load drive 500 pF
ISC Short-circuit current Continuous to common –40, +5 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 1 150 kHz
G = 10 35
G = 100 3.5
G = 1000 350 Hz
SR Slew rate VS = 5 V, VO = 4-V step G = 1 0.16 V/μs
G = 100 0.05
tS Settling time to 0.01% VSTEP = 4 V G = 1 50 μs
G = 100 400
Settling time to 0.001% VSTEP = 4 V G = 1 60
G = 100 500
Overload recovery 50% overdrive 75 μs
REFERENCE INPUT
RIN Input impedance 300 kΩ
Voltage range V– V+ V
POWER SUPPLY
IQ Quiescent current  VIN = VS / 2 50 75 μA
TA = –40°C to +125°C 80
(1) Total VOS, referred-to-input = (VOSI) + (VOSO / G).
(2) RTI = Referred-to-input.
(3) Does not include effects of external resistor RG.