SNIS234A October   2023  – June 2024 ISOTMP35-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Insulation Specification
    6. 5.6  Power Ratings
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Features Description
      1. 6.3.1 Integrated Isolation Barrier and Thermal Response
      2. 6.3.2 Analog Output
        1. 6.3.2.1 Common Mode Transient Immunity (CMTI)
      3. 6.3.3 Thermal Response
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Output Voltage Linearity
      2. 7.1.2 Load Regulation
      3. 7.1.3 Start-Up Settling Time
      4. 7.1.4 Thermal Response
      5. 7.1.5 External Buffer
      6. 7.1.6 ADC Selection and Impact on Accuracy
      7. 7.1.7 Implementation Guidelines
      8. 7.1.8 PSRR
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DFQ|7
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.8 PSRR

Depending on the application, there can be a significant amount of high frequency noise on the power supply line. If high frequency noise (>100kHz) is present, the user can switch to a 1μF bypass capacitor to provide additional filtering on the power supply line. Increasing the bypass capacitance or choosing a capacitor with a lower ESR across frequency improves PSRR performance.

An additional power supply consideration is line regulation. For the ISOTMP35-Q1, line regulation refers to the change in output temperature with changing power supply. Figure 5-6 shows that, across the entire environment temperature range, ISOTMP35-Q1 maintains a steady amount change in temperature across VDD.