SNIS234 October   2023 ISOTMP35-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specification
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Features Description
      1. 7.3.1 Integrated Isolation Barrier and Thermal Response
      2. 7.3.2 Analog Output
      3. 7.3.3 Thermal Response
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Voltage Linearity
      2. 8.1.2 Load Regulation
      3. 8.1.3 Start-Up Settling Time
      4. 8.1.4 Thermal Response
      5. 8.1.5 External Buffer
      6. 8.1.6 ADC Selection and Impact on Accuracy
      7. 8.1.7 Implementation Guidelines
      8. 8.1.8 PSRR
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DFQ|7
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Thermal Information

THERMAL METRIC(1) ISOTMP35-Q1 UNIT
DFQ (SOIC)
7 PINS
RθJA Junction-to-ambient thermal resistance 116.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 62.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 38.8 °C/W
RθJB Junction-to-board thermal resistance 41.9 °C/W
ψJT Junction-to-top characterization parameter 38.3 °C/W
ψJB Junction-to-board characterization parameter N/A °C/W
MT Thermal Mass 51.0 mJ/°C
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.