8.1.10 Control Loop Compensation

The LM27402 voltage mode control system incorporates input voltage feedforward to eliminate the input voltage dependence of the PWM modulator gain. Input voltage feedforward is essential for stability across the entire input voltage range and makes it easier for the designer to select the compensation and power train components. The following describes how to set the output voltage and obtain the open-loop transfer function.

During steady state operation, the DC output voltage is set by the feedback resistor network between V_OUT, FB and GND. The FB voltage is nominally 0.6 V ±1%. The equation describing the output voltage is:

Equation 14.

A good starting value for R_FB1 is 20 kΩ. If an output voltage of 0.6 V is required, R_FB2 must not be used.

There are three main blocks of a voltage-mode buck switcher that the power supply designer needs to consider when designing the control system: power train, PWM modulator, and compensator. A diagram representing the control loop is shown in Figure 35.

Figure 35. Control Loop Schematic Diagram

The power train consists of the filter inductor (L) with DCR (R_DCR), output capacitor (C_OUT) with ESR (effective series resistance R_ESR), and effective load resistance (R_O). The error amplifier (EA) regulates the feedback (FB) voltage to 0.6V. The passive compensation components around the error amplifier establish system stability. Type-III compensation is shown in Figure 35. The PWM modulator establishes the duty cycle command by comparing the error amplifier output (COMP) with an internally generated ramp set at the switching frequency.

The modulator gain, power train and compensator transfer functions must be taken into consideration when obtaining the total open-loop transfer function. The PWM modulator adds a DC gain component to the open-loop transfer function. In a basic voltage-mode system, the PWM gain varies with input voltage. However the LM27402 internal voltage feedforward circuitry maintains a constant PWM gain of 7:

Equation 15.

The power train transfer function includes the filter inductor and its DCR, output capacitor with ESR, and load resistance. The inductor and capacitor create two complex poles at a frequency described by:

Equation 16.

A left half plane zero is created by the output capacitor ESR located at a frequency described by:

Equation 17.

The complete power train transfer function is:

Equation 18.

Figure 36 shows the bode plot of the above transfer function.

Figure 36. Powertrain Bode Plot

The complex poles (f_LC) created by the filter inductor and output capacitor cause a 180° phase shift as seen in Figure 36. The phase is boosted back up to -90° by virtue of the output capacitor ESR zero. The phase shift caused by the complex poles must be compensated to stabilize the loop response. The compensation network shown around the error amplifier in Figure 35 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies optimizes the loop response. The compensator transfer function is:

Equation 19.

The pole located at the origin provides high DC gain to maximize DC load regulation performance. The other two poles and two zeros are strategically located to stabilize the voltage-mode loop depending on the power stage complex poles and damping characteristic, Q. Figure 37 illustrates a typical compensation transfer function.

Figure 37. Type-lll Compensation Network Bode Plot

K_m is the mid-band gain of the compensator and is estimated by:

Equation 20.

f_C is the desired crossover frequency and is normally selected between one tenth and one fifth of the switching frequency, f_SW. The next set of equations show pole and zero locations expressed in terms of the components in the compensator feedback loop.

Equation 21.

Depending on Q, the complex double pole causes an increase in gain at the LC resonant frequency and a precipitous drop in phase. To compensate for the phase drop, it is common practice to place both compensator zeros created by the Type-III compensation network at or slightly below the LC double pole frequency. The other two poles are located beyond this point. One pole is located at the zero caused by the output capacitor ESR and the other pole is placed at half the switching frequency to roll off the higher frequency response.

Equation 22.

Conservative values for the compensation components are found by using the following equations.

Equation 23.

Once the compensation components are fixed, create a Bode plot of the loop response using all three transfer functions. Figure 38 provides an illustration of the loop response.

Figure 38. Loop Response

It is important to always verify the stability by either observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage-mode controlled systems. Excessive phase margin causes slow system response to load transients whereas low phase margin is indicated by an oscillatory load transient response. If the peak voltage deviation is larger than desired, increase f_C and recalculate the compensation components. If this amounts to a reduction in phase margin, the remaining option is to increase output capacitance.