SNVS088F May   2004  – April 2016 LM3704

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Reset Output
      2. 6.3.2 Reset Threshold
      3. 6.3.3 Manual Reset Input (MR)
      4. 6.3.4 Power-Fail Comparator (PFI/PFO)
      5. 6.3.5 Low-Line Output (LLO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 RESET Output Low
      2. 6.4.2 RESET Output High
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 System Examples
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 Overview

The LM3704 microprocessor supervisory circuit monitors power supplies and battery-controlled functions in systems and does not require external components. There is a standard reset threshold voltage of 3.08 V while other custom reset threshold voltages are available to provide maximum monitoring flexibility. The RESET pin pulses low for the reset time-out period when triggered and stays low whenever VCC is below the reset threshold or when MR is below VMRT. Once the VCC rises above the reset threshold, or after MR input rises above VMRT, the RESET pin remains low for the reset timeout period before coming up.

6.2 Functional Block Diagram

LM3704 10136926.gif

6.3 Feature Description

6.3.1 Reset Output

The reset input of a µP initializes the device into a known state. The LM3704 microprocessor supervisory circuit asserts a forced reset output to prevent code execution errors during power-up, power-down, and brownout conditions.

RESET is ensured valid for VCC > 1 V. Once VCC exceeds the reset threshold, an internal timer maintains the output for the reset time-out period. After this interval, reset goes high. The LM3704 offers an active-low RESET.

Any time VCC drops below the reset threshold (such as during a brownout), the reset activates. When VCC again rises above the reset threshold, the internal timer starts. Reset holds until VCC exceeds the reset threshold for longer than the reset time-out period. After this time, reset releases.

The Manual Reset input (MR) initiates a forced reset also. See Manual Reset Input (MR).

6.3.2 Reset Threshold

The LM3704 is available with a reset voltage of 3.08 V. Other reset thresholds in the 2.20-V to 5-V range, in steps of 10 mV, are available; contact Texas Instruments for details.

6.3.3 Manual Reset Input (MR)

Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input is fully debounced and provides an internal 56-kΩ pullup. When the MR input is pulled below VMRT (1.225 V) for more than 25 µs, reset is asserted after a typical delay of 12 µs. Reset remains active as long as MR is held low, and releases after the reset time-out period expires after MR rises above VMRT. Use MR with digital logic to assert or to daisy chain supervisory circuits. It may be used as another low-line comparator by adding a buffer.

6.3.4 Power-Fail Comparator (PFI/PFO)

The PFI is compared to a 1.225-V internal reference, VPFT. If PFI is less than VPFT, the Power-Fail Output (PFO) drops low. The power-fail comparator signals a falling power supply, and is driven typically by an external voltage divider that senses either the unregulated supply or another system supply voltage. The voltage divider generally is chosen so the voltage at PFI drops below VPFT several milliseconds before the main supply voltage drops below the reset threshold, providing advanced warning of a brownout.

The voltage threshold is set by R1 and R2 and is calculated with Equation 1.

Equation 1. LM3704 10136906.gif

NOTE

This comparator is completely separate from the rest of the circuitry, and may be employed for other functions as needed.

6.3.5 Low-Line Output (LLO)

The low-line output comparator is typically used to provide a non-maskable interrupt to a µP when VCC begins falling. LLO monitors VCC and goes low when VCC falls below VLLOT (typically 1.02 × VRST) with hysteresis of 0.0032 × VRST.

6.4 Device Functional Modes

6.4.1 RESET Output Low

Anytime VCC drops below the reset threshold, the RESET output drops low and remains low until VCC rises above the threshold and the reset time-out period has expired. The manual reset input (MR) also causes the reset to be active. If MR input is pulled below VMRT for more than 25 µs, the RESET output drops low and remains low until MR rises above the manual reset threshold (VMRT) and the reset time-out period has expired.

6.4.2 RESET Output High

The RESET output remains high as long as VCC is above the reset threshold and MR is above the manual reset threshold (VMRT).