SNAS558N January   2000  – March 2024 LMC555

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Power Dissipation
      2. 7.3.2 Various Packages and Compatibility
      3. 7.3.3 Operates in Both Astable and Monostable Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Monostable Operation
      2. 7.4.2 Astable Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Flash LED in Monostable Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Frequency Divider
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 Pulse Width Modulator
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curve
      4. 8.2.4 Pulse Position Modulator
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Application Curve
      5. 8.2.5 50% Duty Cycle Oscillator
        1. 8.2.5.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • YPB|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-ACBC8B54-EE28-4674-B01C-6FA9C7F28295-low.pngFigure 4-1 D Package, 8-Pin SOIC,
DGK Package, 8-Pin VSSOP,
and P Package, 8-Pin PDIP (Top View)
GUID-2F007279-13A2-4DCA-92BC-98B69D0EDCC6-low.pngFigure 4-2 YPB Package, 8-Pin DSBGA (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
D (SOIC), DGK (VSSOP), P (PDIP) YPB (DSBGA)
CONTROL VOLTAGE 5 C1 Input Control voltage controls the threshold and trigger levels. This pin determines the pulse duration of the output waveform. An external voltage applied to this pin can also be used to modulate the output waveform.
DISCHARGE 7 A1 Input Open collector output that discharges a capacitor between intervals (in phase with output). This pin toggles the output from high to low when voltage reaches 2/3 of the supply voltage (V+).
GROUND 1 A3 Power Ground reference voltage
OUTPUT 3 C3 Output Output driven waveform
RESET 4 C2 Input Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, connect this pin to V+ to avoid false triggering.
THRESHOLD 6 B1 Input Compares the voltage applied to the pin with a reference voltage of 2/3 V+. The amplitude of voltage applied to this pin is responsible for the set state of the flip-flop.
TRIGGER 2 B3 Input Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin.
V+ 8 A2 Power Supply voltage with respect to ground