SNOSDF9B July   2023  – March 2024 LMG2100R044

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Slew Rate Control
        4. 8.2.2.4 Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RAR|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

The LMG2100R044 operates in normal mode and UVLO mode. See Section 7.3.2 for information on UVLO operation mode. In the normal mode, the output state is dependent on the states of the HI and LI pins. Table 7-3 lists the output states for different input pin combinations. Note that when both HI and LI are asserted, both GaN FETs in the power stage are turned on. Careful consideration must be applied to the control inputs in order to avoid this state, as it will result in a shoot-through condition, which can permanently damage the device.

Table 7-3 Truth Table
HILIHIGH-SIDE GaN FETLOW-SIDE GaN FETSW
LLOFFOFFHi-Z
LHOFFONPGND
HLONOFFVIN
HHONON- - -