SNOSD91B March   2019  – February 2020

PRODUCTION DATA.

1. Features
2. Applications
3. Description
1.     Device Images
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Parameter Measurement Information
8. Detailed Description
1. 8.1 Overview
2. 8.2 Functional Block Diagram
3. 8.3 Feature Description
4. 8.4 Safe Operation Area (SOA)
9. Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
1. 9.2.1 Design Requirements
2. 9.2.2 Detailed Design Procedure
3. 9.3 Dos and Don'ts
10. 10Power Supply Recommendations
1. 10.1 Using an Isolated Power Supply
2. 10.2 Using a Bootstrap Diode
11. 11Layout
1. 11.1 Layout Guidelines
2. 11.2 Layout Example
12. 12Device and Documentation Support
13. 13Mechanical, Packaging, and Orderable Information

• RWH|32

#### 8.4.1 Repetitive SOA

The allowed repetitive SOA for the LMG341xR150 (Figure 12) is defined by the peak drain current (IDS) and the drain to source voltage (VDS) of the device during turn on. The peak drain current during switching is the sum of several currents going into drain terminal: the inductor current (Iind); the current required to charge the COSS of the other GaN device in the totem pole; and the current required to charge the parasitic capacitance (Cpar) on the switching node. 47 pF is used as an average COSS of the device during switching. The parasitic capacitance on the switch node may be estimated by using the overlap capacitance of the PCB. A boost topology is used for the SOA testing. The circuit shown in Figure 19 is used to generate the SOA curve in Figure 12. For reliable operation, the junction temperature of the device must also be limited to 125 °C. The IDS of Figure 12 can be calculated by:

IDS = Iind + (47 pF + Cpar) × Drain slew rate at peak current

where

• drain slew rate at the peak current is estimated between 70 percent and 30 percent of the bus voltage
• Cpar is the parasitic board capacitance at the switched node