SNAS573D January   2012  – September 2021 LMK01801

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
    1. 5.1 Functional Configurations
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Serial MICROWIRE Timing Diagram
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  High-Speed Clock Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
      2. 9.3.2  Clock Distribution
      3. 9.3.3  Small Divider (1 to 8)
      4. 9.3.4  Large Divider (1 to 1045)
      5. 9.3.5  CLKout Analog Delay
      6. 9.3.6  CLKout0 to CLKout11 Digital Delay
      7. 9.3.7  CLKout12 and CLKout13 Digital Delay
      8. 9.3.8  Programmable Outputs
      9. 9.3.9  Clock Output Synchronization
      10. 9.3.10 Default Clock Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Programmable Mode
      2. 9.4.2 Pin Control Mode
      3. 9.4.3 Inputs / Outputs
        1. 9.4.3.1 CLKin0 and CLKin1
      4. 9.4.4 Input and Output Dividers
      5. 9.4.5 Fixed Digital Delay
        1. 9.4.5.1 Fixed Digital Delay - Example
      6. 9.4.6 Clock Output Synchronization (SYNC)
        1. 9.4.6.1 Dynamically Programming Digital Delay
          1. 9.4.6.1.1 Relative Dynamic Digital Delay
          2. 9.4.6.1.2 Relative Dynamic Digital Delay - Example
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 Overview
    6. 9.6 Register Map
      1. 9.6.1 Default Device Register Settings After Power On/Reset
      2. 9.6.2 Register R0
        1. 9.6.2.1 RESET
        2. 9.6.2.2 POWERDOWN
        3. 9.6.2.3 CLKoutX_Y_PD
          1. 9.6.2.3.1 CLKinX_BUF_TYPE
          2. 9.6.2.3.2 CLKinX_DIV
          3. 9.6.2.3.3 CLKinX_MUX
      3. 9.6.3 Register R1 and R2
        1. 9.6.3.1 CLKoutX_TYPE
      4. 9.6.4 Register R3
        1. 9.6.4.1 CLKout12_13_ADLY
        2. 9.6.4.2 CLKout12_13_HS, Digital Delay Half Shift
        3. 9.6.4.3 SYNC1_QUAL
        4. 9.6.4.4 SYNCX_POL_INV
        5. 9.6.4.5 NO_SYNC_CLKoutX_Y
        6. 9.6.4.6 CLKoutX_Y_OFFSET_PD
        7. 9.6.4.7 SYNCX_FAST
        8. 9.6.4.8 SYNCX_AUTO
      5. 9.6.5 Register R4
        1. 9.6.5.1 CLKout12_13_DDLY, Clock Channel Digital Delay
      6. 9.6.6 Register R5
        1. 9.6.6.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay
        2. 9.6.6.2 CLKoutX_Y_DIV Clock Output Divide
      7. 9.6.7 Register 15
        1. 9.6.7.1 uWireLock
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
        1. 10.1.1.1 Driving CLKin Inputs
          1. 10.1.1.1.1 Driving CLKin Pins With a Differential Source
          2. 10.1.1.1.2 Driving CLKin Pins With a Single-Ended Source
        2. 10.1.1.2 Termination and Use of Clock Output (Drivers)
          1. 10.1.1.2.1 Termination for DC-Coupled Differential Operation
          2. 10.1.1.2.2 Termination for AC-Coupled Differential Operation
          3. 10.1.1.2.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pin Connection Recommendations
        1. 12.1.1.1 Vcc Pins and Decoupling
        2. 12.1.1.2 Unused clock outputs
        3. 12.1.1.3 Unused clock inputs
        4. 12.1.1.4 Unused GPIO (CLKoutTYPE_X)
        5. 12.1.1.5 Bias
        6. 12.1.1.6 In MICROWIRE Mode
    2. 12.2 Thermal Management
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CURRENT CONSUMPTION
ICC_PDPower Down Supply Current1mA
ICC_CLKSSupply Current with all clocks enabled (2)All clock delays disabled,
CLKoutX_Y_DIV = 1,
CLKoutX_TYPE = 1 (LVDS),
313390mA
CLKin0/0* AND CLKin1/1* INPUT CLOCK SPECIFICATIONS
fCLKinXClock 0 or 1 Input FrequencyCLKinX_MUX = Bypassed
CLKoutX_Y_DIV = 1
0.0013100MHz
CLKinX_MUX = Bypassed
CLKoutX_Y_DIV = 2 to 8
0.0011600MHz
CLKin_MUX = Divide
CLKinX_DIV = 2 to 8
0.0013100MHz
SLEWCLKinSlew Rate on CLKin (3)20% to 80%0.150.5V/ns
DUTYCLKinClock input duty cycle50%
VCLKinClock Input,
Single-ended Input Voltage
AC coupled to CLKinX; CLKinX* AC coupled to Ground
(CLKinX_BUF_TYPE = Bipolar
0.252.4Vpp
AC coupled to CLKinX; CLKinX* AC coupled to Ground
(CLKinX_BUF_TYPE = MOS
0.252.4Vpp
VIDCLKinClock Input
Differential Input Voltage (1)(9)
AC coupled
(CLKinX_BUF_TYPE = Bipolar
0.251.55|V|
VSSCLKin0.53.1Vpp
VIDCLKinAC coupled
(CLKinX_BUF_TYPE = MOS
0.251.55|V|
VSSCLKin0.53.1Vpp
VCLKinX-offsetDC offset voltage between CLKinX/CLKinX*
CLKinX* - CLKinX
Each pin AC coupled CLKinX_BUF_TYPE = Bipolar0mV
0mV
VCLKin- VIHMaximum input voltageDC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = MOS2.0VCCV
VCLKin- VILMinimum input voltage0.00.4V
VCLKinX-offsetDC offset voltage between CLKinX/CLKinX*
CLKinX* - CLKinX
Each pin AC coupled CLKinX_BUF_TYPE = MOS55mV
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire) for EN_PIN_CTRL = MIDDLE
VIHHigh-Level Input Voltage1.2VCCV
VILLow-Level Input Voltage0.4V
IIHHigh-Level Input CurrentVIH = VCC-55µA
IILLow-Level Input CurrentVIL = 0-55µA
DIGITAL INPUTS (SYNC0, SYNC1) FOR EN_PIN_CTRL = MIDDLE
VIHHigh-Level Input Voltage1.2VCCV
VILLow-Level Input Voltage0.4V
IIHHigh-Level Input Current
VIH = VCC
VIH = VCC-55µA
IILLow-Level Input Current
VIL = 0 V
VIL = 0-40-5µA
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire, SYNC0, SYNC1) FOR EN_PIN_CTRL= LOW OR HIGH
VIHHigh-Level Input Voltage2.6VCCV
VIMMid-Level Input Voltage1.31.85V
VILLow-Level Input Voltage0.7V
IIHHigh-Level Input CurrentVIH = VCC100µA
IIMMid-Level Input Current-1010µA
IILLow-Level Input CurrentVIL= 0-100µA
CLOCK SKEW AND DELAY
TPDCLKinX to CLKoutYSingle-ended CLKinX* input, LVDS output2.25ns
TSKEWCLKoutX to CLKoutY
(4)(5)
LVDS-to-LVDS, T = 25°C,
FCLK = 800 MHz, RL= 100 Ω
AC coupled, Within same Divider
3ps
LVPECL-to-LVPECL, T = 25°C
FCLK = 800 MHz, RL= 100 Ω
emitter resistors = 240 Ω to GND
AC coupled, Within same Divider
3
Skew between any two LVCMOS outputs, same CLKout or different CLKout (4)(5)RL = 50 Ω, CL = 10 pF,
T = 25 °C, FCLK = 100 MHz, Within same Divider
50
MixedTSKEW CLKoutX - CLKoutYLVPECL to LVDS skewSame device, T = 25°C,
250 MHz, Within same Divider
32ps
LVDS to LVCMOS skew830
LVCMOS to LVPECL skew800
FADLYMaximum Analog
Delay Frequency
1536MHz
LVDS CLOCK OUTPUTS (CLKoutX)
fCLKoutMaximum Clock Frequency
(5)(6)
RL = 100 Ω1600MHz
VODDifferential Output Voltage
(1)(9)
T = 25°C, DC measurement
AC coupled to receiver input
R = 100 Ω differential termination
225400575mV
ΔVODChange in Magnitude of VOD for complementary output states-5050mV
VOSOutput Offset Voltage1.1251.251.375V
ΔVOSChange in VOS for complementary output states35|mV|
TROutput Rise Time20% to 80%, RL = 100 Ω200ps
TFOutput Fall Time80% to 20%, RL = 100 Ω300ps
ISA
ISB
Output short circuit current - single endedSingle-ended output shorted to GND, T = 25°C-2424mA
ISABOutput short circuit current - differentialComplimentary outputs tied together-1212mA
LVPECL CLOCK OUTPUTS (CLKoutX)
TROutput Rise Time20% to 80%, RL = 100 Ω,
emitter resistors = 240 Ω to GND
200ps
TFOutput Fall Time80% to 20%, RL = 100 Ω,
emitter resistors = 240 Ω to GND
200ps
LOW COMMON-MODE VOLTAGE PECL (LCPECL)(7), (8)
fCLKoutMaximum Clock Frequency
(5)(6)
RL = 100 Ω,
emitter resistors = 240 Ω to GND
3100MHz
VOHOutput High VoltageT = 25°C, DC Measurement
Termination = 50 Ω to
VCC - 0.6 V
1.6V
VOLOutput Low Voltage0.75V
VODOutput Voltage5358401145mV
1600-mV LVPECL (LVPECL) CLOCK OUTPUTS (CLKoutX)
fCLKoutMaximum Clock Frequency
(5)(6)
RL = 100 Ω,
emitter resistors = 240 Ω to GND
3100MHz
VOHOutput High VoltageT = 25°C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V
VCC - 0.94V
VOLOutput Low VoltageVCC - 1.9V
VODOutput Voltage5859251240mV
2000-mV LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX)
fCLKoutMaximum Clock Frequency
(5)(6)
RL = 100 Ω,
emitter resistors = 240 Ω to GND
3100MHz
VOHOutput High VoltageT = 25°C, DC Measurement
Termination = 50 Ω to
VCC - 2.3 V
VCC - 0.97V
VOLOutput Low VoltageVCC - 1.95V
VODOutput Voltage70511501585mV
LVCMOS CLOCK OUTPUTS (CLKoutX)
fCLKoutMaximum Clock Frequency
(5)(6)
5-pF Load250MHz
VOHOutput High Voltage1-mA LoadVCC - 0.1V
VOLOutput Low Voltage1-mA Load0.1V
IOHOutput High Current (Source)VCC = 3.3 V, VO = 1.65 V28mA
IOLOutput Low Current (Sink)VCC = 3.3 V, VO = 1.65 V28mA
DUTYCLKOutput Duty Cycle
(5)
VCC/2 to VCC/2, FCLK = 100 MHz, T = 25 °C45%50%55%
TROutput Rise Time20% to 80%, RL = 50 Ω,
CL = 5 pF
400ps
TFOutput Fall Time80% to 20%, RL = 50 Ω,
CL = 5 pF
400ps
MICROWIRE INTERFACE TIMING
TECSLE to Clock Set Up TimeSee MICROWIRE Input Timing25ns
TDCSData to Clock Set Up TimeSee MICROWIRE Input Timing25ns
TCDHClock to Data Hold TimeSee MICROWIRE Input Timing8ns
TCWHClock Pulse Width HighSee MICROWIRE Input Timing25ns
TCWLClock Pulse Width LowSee MICROWIRE Input Timing25ns
TCESClock to LE Set Up TimeSee MICROWIRE Input Timing25ns
TEWHLE Pulse WidthSee MICROWIRE Input Timing25ns
See applications section Section 8.1 for definition of VID and VOD voltages.
For Icc for specific part configuration, see applications section Section 11.1 for calculating Icc.
The minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
Ensured by characterization.
Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.
For LCPECL, the common mode voltage is regulated (VOH=1.6V, VOL=VOH-Vsw, Vcm=(VOH+VOL)/2 ) and is more stable against with PVT (process, supply, temperature) variations than conventional LVPECL implementations..
With proper selection of external emitter resistors, LCPECL can also be used for DC-coupling with devices with low common voltage such as 0.5V or 0.8V etc.
Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for more information.