SNAS855C November   2023  – May 2024 LMKDB1108 , LMKDB1120 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3 LMKDB1204 Registers

Table 9-51 lists the memory-mapped registers for the LMKDB1204 registers. All register offset addresses not listed in Table 9-51 must be considered as reserved locations and the register contents must not be modified.

Table 9-51 LMKDB1204 Registers
OffsetAcronymRegister NameSection
0hR0Output Enable Control for CLK2 and CLK3Section 9.3.1
1hR1Output Enable Control for CLK0 and CLK1Section 9.3.2
2hR2OE Pin Readback for CLK2 and CLK3Section 9.3.3
3hR3OE Pin Readback for CLK0 and CLK1Section 9.3.4
4hR4CLKIN1 AOD Enable ControlSection 9.3.5
5hR5Device InfoSection 9.3.6
6hR6Device Info (cont.)Section 9.3.7
7hR7SMBus Byte CounterSection 9.3.8
11hR17Output AmplitudeSection 9.3.9
12hR18Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS ReadbackSection 9.3.10
14hR20Output Slew Rate Select MSB for CLK2 and CLK3Section 9.3.11
15hR21Output Slew Rate Select MSB for CLK0 and CLK1Section 9.3.12
24hR36CLKIN0 AOD Enable ControlSection 9.3.13
26hR38Non-clearable SMBUS Write LockSection 9.3.14
27hR39LOS Event Status and Clearable SMBus Write LockSection 9.3.15
2BhR43CLKIN Source SelectSection 9.3.16
5BhR91Slew Rate Speed Options 1 and 2 AssignmentsSection 9.3.17
5ChR92Slew Rate Speed Options 3 and 4 AssignmentsSection 9.3.18
5DhR93CLKIN0 AC/DC coupled SelectionSection 9.3.19
62hR98Output Slew Rate Select LSB for CLK0 and CLK1Section 9.3.20
63hR99Output Slew Rate Select LSB for CLK2 and CLK3Section 9.3.21

Complex bit access types are encoded to fit into small table cells. Table 9-52 shows the codes that are used for access types in this section.

Table 9-52 LMKDB1204 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W
1C		 Write
1 to clear
Reset or Default Value
-n Value after reset or the default value

9.3.1 R0 Register (Offset = 0h) [Reset = 28h]

R0 is shown in Table 9-53.

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Table 9-53 R0 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 CLK_EN_2 R/W 1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
4 RESERVED R 0h Reserved
3 CLK_EN_3 R/W 1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
2:0 RESERVED R 0h Reserved

9.3.2 R1 Register (Offset = 1h) [Reset = 14h]

R1 is shown in Table 9-54.

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Table 9-54 R1 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 CLK_EN_0 R/W 1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled
3 RESERVED R 0h Reserved
2 CLK_EN_1 R/W 1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
1:0 RESERVED R 0h Reserved

9.3.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 9-55.

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Table 9-55 R2 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 RB_OEb_2 R 0h Status of OEb2
4 RESERVED R 0h Reserved
3 RB_OEb_3 R 0h Status of OEb3
2:0 RESERVED R 0h Reserved

9.3.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 9-56.

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Table 9-56 R3 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 RB_OEb_0 R 0h Status of OEb0
3 RESERVED R 0h Reserved
2 RB_OEb_1 R 0h Status of OEb1
1:0 RESERVED R 0h Reserved

9.3.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 9-57.

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Table 9-57 R4 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 CLKIN1_AOD_ENABLE R/W 1h Enable automatic output disable (AOD) for CLKIN1 to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive
1h = Active
3:0 RESERVED R 0h Reserved

9.3.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 9-58.

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Table 9-58 R5 Register Field Descriptions
Bit Field Type Reset Description
7:4 REV_ID R 0h Revision ID
3:0 VENDOR_ID R Ah Vendor ID

9.3.7 R6 Register (Offset = 6h) [Reset = 24h]

R6 is shown in Table 9-59.

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Table 9-59 R6 Register Field Descriptions
Bit Field Type Reset Description
7:0 DEV_ID R 24h Device ID

9.3.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 9-60.

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Table 9-60 R7 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4:0 SMBUS_BC R/W 7h SMBUS Block Read Byte Count

9.3.9 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 9-61.

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Table 9-61 R17 Register Field Descriptions
Bit Field Type Reset Description
7:4 AMP_1 R/W 6h Global Differential output Control,approximately 0.6 V to 1 V 25 mV/step (default = 0.75 V)
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV
3:0 AMP_0 R/W 6h Global Differential output Control, approximately 0.6 V to 1 V 25 mV/step (default = 0.75 V)
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV

9.3.10 R18 Register (Offset = 12h) [Reset = 0Ah]

R18 is shown in Table 9-62.

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Table 9-62 R18 Register Field Descriptions
Bit Field Type Reset Description
7 RX_CLKIN1_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN1 is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input
6 RX_CLKIN1_EN_RTERM R/W 0h Enable termination resistors on CLKIN1
0h = Input termination inactive
1h = Input termination active
5 RX_CLKIN0_EN_RTERM R/W 0h Enable termination resistors on CLKIN0
0h = Input termination inactive
1h = Input termination active
4 RESERVED R 0h Reserved
3 PD_RESTOREB R 1h Save configuration in powerdown
0h = Config Cleared
1h = Config Saved
2 RESERVED R 0h Reserved
1 SDATA_TIMEOUT_EN R 1h Enable SMBus SDATA time out monitoring
0h = Disable SDATA timeout
1h = Enable SDATA timeout
0 LOSb_RB R 0h Real time read back of loss detect block output
0h = LOS Event Detected
1h = LOS Event Not-Detected

9.3.11 R20 Register (Offset = 14h) [Reset = 28h]

R20 is shown in Table 9-63.

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Table 9-63 R20 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SLEWRATE_SEL_CLK2_MSB R/W 1h MSB CLK2 slew rate select
4 RESERVED R 0h Reserved
3 SLEWRATE_SEL_CLK3_MSB R/W 1h MSB CLK3 slew rate select
2:0 RESERVED R 0h Reserved

9.3.12 R21 Register (Offset = 15h) [Reset = 14h]

R21 is shown in Table 9-64.

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Table 9-64 R21 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 SLEWRATE_SEL_CLK0_MSB R/W 1h MSB CLK0 slew rate select
3 RESERVED R 0h Reserved
2 SLEWRATE_SEL_CLK1_MSB R/W 1h MSB CLK1 slew rate select
1:0 RESERVED R 0h Reserved

9.3.13 R36 Register (Offset = 24h) [Reset = 09h]

R36 is shown in Table 9-65.

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Table 9-65 R36 Register Field Descriptions
Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
3 CLKIN0_AOD_ENABLE R/W 1h Enable automatic output disable (AOD) for CLKIN0 to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive
1h = Active
2:0 RESERVED R 0h Reserved

9.3.14 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 9-66.

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Table 9-66 R38 Register Field Descriptions
Bit Field Type Reset Description
7:1 RESERVED R 0h Reserved
0 WRITE_LOCK R 0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.3.15 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 9-67.

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Table 9-67 R39 Register Field Descriptions
Bit Field Type Reset Description
7:2 RESERVED R 0h Reserved
1 LOS_EVT R 0h LOS Event Status. When high, indicates that a LOS event is detected. Can be cleared by writing a 1.
0h = Not LOS Event Detected
1h = LOS Event Detected
0 WRITE_LOCK_RW1C R/W1C 0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers can not be written to. This bit can be cleared by writing a 1.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.3.16 R43 Register (Offset = 2Bh) [Reset = 00h]

R43 is shown in Table 9-68.

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Table 9-68 R43 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5:4 CLKIN_SEL R/W 0h CLKIN Source Select
0h = All outputs come from CLKIN0
1h = CLKIN0 inputs go to BANK0 and CLKIN1 inputs go to BANK1
2h = Invalid
3h = All outputs come from CLKIN1
3:0 RESERVED R 0h Reserved

9.3.17 R91 Register (Offset = 5Bh) [Reset = 60h]

R91 is shown in Table 9-69.

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Table 9-69 R91 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_2 R/W 6h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
3:0 SLEWRATE_OPT_1 R/W 0h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)

9.3.18 R92 Register (Offset = 5Ch) [Reset = FAh]

R92 is shown in Table 9-70.

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Table 9-70 R92 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_4 R/W Fh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
3:0 SLEWRATE_OPT_3 R/W Ah There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)

9.3.19 R93 Register (Offset = 5Dh) [Reset = 00h]

R93 is shown in Table 9-71.

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Table 9-71 R93 Register Field Descriptions
Bit Field Type Reset Description
7:1 RESERVED R 0h Reserved
0 RX_CLKIN0_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN0 is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input

9.3.20 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 9-72.

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Table 9-72 R98 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SLEWRATE_SEL_CLK1_LSB R/W 0h LSB CLK1 Slew Rate Control
4 SLEWRATE_SEL_CLK0_LSB R/W 0h LSB CLK0 Slew Rate Control
3:0 RESERVED R 0h Reserved

9.3.21 R99 Register (Offset = 63h) [Reset = 00h]

R99 is shown in Table 9-73.

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Table 9-73 R99 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6 SLEWRATE_SEL_CLK3_LSB R/W 0h LSB CLK3 Slew Rate Control
5:3 RESERVED R 0h Reserved
2 SLEWRATE_SEL_CLK2_LSB R/W 0h LSB CLK2 Slew Rate Control
1:0 RESERVED R 0h Reserved