SNAS855C November   2023  – May 2024 LMKDB1108 , LMKDB1120 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.2 Programmable Output Slew Rate

The LMKDB family supports programmable output slew rate for each individual output. The slew rate can be chosen between 16 different values. There are four register field options, named SLEWRATE_OPT_#, each storing a slew rate value (chosen out of the 16 available slew rate values). A register field assignment of 0x0 is the fastest slew rate setting and a register field assignment of 0xF is the slowest slew rate setting. The SLEWRATE_OPT_# default values are found in Table 8-2. The corresponding ranges for the four default slew rates can be found in Section 6 under CLOCK OUTPUT CHARACTERISTICS - 100 MHz 85 Ω PCIe or CLOCK OUTPUT CHARACTERISTICS - 100 MHz 100 Ω PCIe for the specification Output slew rate. Slew rate is heavily dependent on trace characteristics including trace width, copper thickness, substrate height, dielectric constant, and loss tangent.

Table 8-2 LMKDB Default SLEWRATE_OPT_# Values
Register Field Name Default Value Default Slew Rate
SLEWRATE_OPT_1 0x0 Highest
SLEWRATE_OPT_2 0x6 High (default for all outputs)
SLEWRATE_OPT_3 0xA Low
SLEWRATE_OPT_4 0xF Lowest

Each of these slew rates can be assigned to each output separately using the register bits SLEWRATE_SEL_CLKX_LSB and SLEWRATE_SEL_CLKX_MSB. Setting these two bits assigns the slew rate for a specific output X, as shown in Table 8-3. By default, all outputs are assigned to SLEWRATE_OPT_2.

Table 8-3 SLEWRATE_SEL_CLKX_LSB & SLEWRATE_SEL_CLKX_MSB Slew Rate Selection
SLEWRATE_SEL_CLKX_LSB SLEWRATE_SEL_CLKX_MSB Slew Rate Option Selection
0 0 SLEWRATE_OPT_4
1 0 SLEWRATE_OPT_3
0 1 SLEWRATE_OPT_2
1 1 SLEWRATE_OPT_1

To program the slew rate to the desired slew rate, the following sequence needs to be followed:

  1. [Optional]: if the default assignments shown in Table 8-2 for each slew rate speed is not as desired, one of the slew rate options value can be changed to another slew rate.
  2. Program SLEWRATE_SEL_CLKX_MSB and SLEWRATE_SEL_CLKX_LSB to assign clock output X to desired slew rate speed option, as shown in Table 8-3. The default assignments for each option can be found in Table 8-2.