SNVSAS5 March   2018 LMR23615-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load, VIN = 12 V
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency Peak-Current-Mode Control
      2. 7.3.2  Adjustable Frequency
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  EN/SYNC
      5. 7.3.5  VCC, UVLO
      6. 7.3.6  Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
      7. 7.3.7  Internal Compensation and CFF
      8. 7.3.8  Bootstrap Voltage (BOOT)
      9. 7.3.9  Overcurrent and Short-Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-Forward Capacitor
        7. 8.2.2.7  Input Capacitor Selection
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  VCC Capacitor Selection
        10. 8.2.2.10 Undervoltage Lockout Setpoint
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 EN/SYNC

The voltage on the EN/SYNC pin controls the ON or OFF operation of LMR23615-Q1. A voltage less than 1 V (typical) shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator. The EN pin is an input and cannot be left open or floating. The simplest way to enable the operation of the LMR23615-Q1 is to connect the EN to VIN. This allows self-start-up of the LMR23615-Q1 when VIN is within the operation range.

Many applications benefit from the employment of an enable divider RENT and RENB (Figure 16) to establish a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. An external logic signal can also be used to drive EN input for system sequencing and protection.

LMR23615-Q1 system_UVLO_enable_divider_snvsah2.gifFigure 16. System UVLO by Enable Divider

The EN/SYNC pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the EN/SYNC pin. The AC coupled peak-to-peak voltage at the EN/SYNC pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse detector, and the minimum SYNC clock ON- and OFF-times must be longer than 100 ns (typical). A 3.3-V or a higher amplitude pulse signal coupled through a 1-nF capacitor CSYNC is a good starting point. Keeping RENT // RENB (RENT parallel with RENB) in the 100-kΩ range is a good choice. RENT is required for this synchronization circuit, but RENB can be left unmounted if system UVLO is not needed. LMR23615-Q1 switching action can be synchronized to an external clock from 200 kHz to 2.2 MHz. Figure 18 and Figure 19 show the device synchronized to an external system clock.

LMR23615-Q1 synchronize_external_clock_snvsah2.gifFigure 17. Synchronize to External Clock
LMR23615-Q1 LMR2361DRR-scopeshot-01-time-400ns-div-SNVSAV8.pngFigure 18. Synchronizing in PWM Mode
LMR23615-Q1 LMR2361DRR-scopeshot-02-time-1us-div-SNVSAV8.pngFigure 19. Synchronizing in PFM Mode