SNOSB45F February   2010  – January 2016 LMV7231

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 3.3-V Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Voltage Range Above V+
    4. 7.4 Device Functional Modes
      1. 7.4.1 +IN1 through +IN6 Input Pins
      2. 7.4.2 -IN1 through -IN6 Input Pins
      3. 7.4.3 CO1 through C06 Output Pins
      4. 7.4.4 COPOL Input Pin
      5. 7.4.5 AO Output Pin
      6. 7.4.6 AOSEL Input Pin
      7. 7.4.7 Three-Resistor Voltage Divider Selection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Proper grounding and the use of a ground plane helps to ensure the specified performance of the LMV7231. Minimizing trace lengths, reducing unwanted parasitic capacitance, and using surface-mount components also helps. Comparators are very sensitive to input noise.

  1. Use a printed-circuit-board with a good, unbroken low-inductance ground plane.
  2. Place a decoupling capacitor (0.1-µF ceramic surface mount capacitor) as close to V+ pin as possible.
  3. On the inputs and the outputs, keep lead lengths and the divider resistors as short possible to avoid noise pick-up.

The DAP pad is connected to the bottom of the die and is not designed to carry current. The DAP thermal pad must be connected directly to the GND pin to avoid noise and possible voltage gradients. The primary grounding pin is the GND pin.

10.2 Layout Example

LMV7231 LMV7231_Layout_Exmpl.gif Figure 41. Example Layout