8.2.2.1.1 Enable Divider, R_ENT and R_ENB Selection

The enable input provides a precise 1.18-V reference threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as V_IN. The enable input also incorporates 90 mV (typical) of hysteresis resulting in a falling threshold of 1.09V. The maximum recommended voltage into the EN pin is 6.5 V. For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to limit this voltage.

The function of the R_ENT and R_ENB divider shown in the Functional Block Diagram is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable under voltage lockout. This is often used in battery-powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems such as 24-V AC/DC systems where a lower boundary of operation should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14202H output rail. The two resistors should be chosen based on the following ratio:

The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good practice to use the enable divider and turn on the regulator when V_IN is close to reaching its nominal value. This will ensure smooth start-up and will prevent overloading the input supply.

8.2.2.1.2 Output Voltage Selection

Output voltage is determined by a divider of two resistors connected between V_O and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The high-side MOSFET ON-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at FB is above 0.8 V, ON-time cycles will not occur.

The regulated output voltage determined by the external divider resistors R_FBT and R_FBB is:

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

These resistors should be chosen from values in the range of 1 kΩ to 50 kΩ.

A feed-forward capacitor is placed in parallel with R_FBT to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple.

A table of values for R_FBT , R_FBB , and R_ON is included in the simplified applications schematic.

8.2.2.1.3 Soft-Start Capacitor, C_SS, Selection

Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.

Upon turnon, after all UVLO conditions have been passed, an internal 8-uA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:

This equation can be rearranged as follows:

Use of a 4700-pF capacitor results in 0.5ms soft-start duration. This is a recommended value. Note that high values of C_SS capacitance will cause more output voltage droop when a load transient goes across the DCM-CCM boundary. Use Equation 22 below to find the DCM-CCM boundary load current for the specific operating condition. If a fast load transient response is desired for steps between DCM and CCM mode the soft-start capacitor value should be less than 0.018µF.

As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200 μA current sink:

• The enable input being “pulled low”
• Thermal shutdown condition
• Overcurrent fault
• Internal V_INUVLO

8.2.2.1.4 Output Capacitor, C_O, Selection

None of the required output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst-case RMS current rating of 0.5 x I_{LR P-P}, as calculated in Equation 23. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a minimum value. Low ESR capacitors, such as ceramic and polymer electrolytic capacitors are recommended.

8.2.2.1.5 Input Capacitor, C_IN, Selection

The LMZ14202H module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance should be as close as possible to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by Equation 12:

(As a point of reference, the worst-case ripple current will occur when the module is presented with full load current and when V_IN = 2 x V_O).

Recommended minimum input capacitance is 10-uF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating.

If the system design requires a certain maximum value of input ripple voltage ΔV_IN to be maintained then Equation 13 may be used.

If ΔV_IN is 1% of V_IN for a 24V input to 12V output application this equals 240 mV and f_SW = 400 kHz.

Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines.

8.2.2.1.6 ON-Time, R_ON, Resistor Selection

Many designs will begin with a desired switching frequency in mind. As seen in the Typical Characteristics section, the best efficiency is achieved in the 300kHz-400kHz switching frequency range. Equation 16 can be used to calculate the R_ON value.

This can be rearranged as

The selection of R_ON and f_SW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT Control Circuit Overview section.

The ON-time of the LMZ14202H timer is determined by the resistor R_ON and the input voltage V_IN. It is calculated as follows:

The inverse relationship of t_ON and V_IN gives a nearly constant switching frequency as V_IN is varied. R_ON should be selected such that the ON-time at maximum V_IN is greater than 150 ns. The ON-timer has a limiter to ensure a minimum of 150 ns for t_ON. This limits the maximum operating frequency, which is governed by Equation 19:

This equation can be used to select R_ON if a certain operating frequency is desired so long as the minimum ON-time of 150 ns is observed. The limit for R_ON can be calculated as follows:

If R_ON calculated in Equation 17 is less than the minimum value determined in Equation 20 a lower frequency should be selected. Alternatively, V_IN(MAX) can also be limited in order to keep the frequency unchanged.

Additionally, the minimum OFF-time of 260 ns (typical) limits the maximum duty ratio. Larger R_ON (lower F_SW) should be selected in any application requiring large duty ratio.