SNVS192C October   2002  – November 2015 LP3992

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Input Test Signals
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Shutdown and Enable
      2. 8.3.2 Fast Turnon and Turnoff
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Operation
  9. 9 Application And Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Capacitors
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 No-Load Stability
        5. 9.2.2.5 Capacitor Characteristics
        6. 9.2.2.6 Power Dissipation
        7. 9.2.2.7 Estimating Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The LP3992 device is a CMOS voltage regulator with a low-input operating-voltage tolerance. Key protection circuits, including thermal-overload and short-circuit protection, are integrated in the device. Using the EN pin, the device may be controlled to provide a SHUTDOWN state, in which negligible supply current is drawn. The LP3992 is designed to be stable with space-saving ceramic capacitors.

8.2 Functional Block Diagram

LP3992 fbd_snvs192.gif

8.3 Feature Description

8.3.1 Shutdown and Enable

The LP3992 may be switched ON or OFF by a logic input at the EN pin. A high voltage at the EN pin turns the device on. A low voltage on the EN pin will disable the regulator, and will activate the fast turnoff circuitry to discharge the output capacitance. When the regulator is disabled the device typically consumes 3 nA.

If the application does not require the EN feature, the EN pin must be tied to VIN to keep the regulator output permanently on.

To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under VIL and VIH.

8.3.2 Fast Turnon and Turnoff

The controlled shutdown feature of the device provides a fast turn off by discharging the output capacitor via an internal FET device. This discharge is current limited by the RDSON of this switch. Fast turnon is ensured by control circuitry within the reference block allowing a very fast ramp of the output voltage to reach the target voltage.

8.4 Device Functional Modes

8.4.1 Enable Operation

The LP3992 may be switched ON or OFF by a logic input at the EN pin. A high voltage at the EN pin turns the device on. A low voltage on the EN pin will disable the regulator, and will activate the fast turnoff circuitry to discharge the output capacitance. When the regulator is disabled the device typically consumes 3 nA.

If the application does not require the EN feature, the EN pin should be tied to VIN to keep the regulator output permanently on.

To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under VIL and VIH.