SBOS690A July   2016  – December 2019 OPA2626

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      SAR ADC Driver
      2.      High Fidelity Topology Improves Dynamic Performance (fIN = 10-kHz, 1-MSPS FFT)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: OPA2626
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: High-Supply
    6. 6.6 Electrical Characteristics: Low-Supply
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 DC Parameter Measurements
    2. 7.2 Transient Parameter Measurements
    3. 7.3 AC Parameter Measurements
    4. 7.4 Noise Parameter Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SAR ADC Driver
      2. 8.3.2 Electrical Overstress
    4. 8.4 Device Functional Modes
      1. 8.4.1 High-Drive Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
        2. 12.1.1.2 TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Detailed Design Procedure

An ADC input driver circuit consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input voltage and the low output impedance provides a buffer between the signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-capacitor input stage of the ADC and acts as an antialiasing filter to band-limit the wideband noise contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the circuit, driven by the following requirements:

  • The RFLT and CFLT filter bandwidth must be low to band-limit the noise fed into the input of the ADC, thereby increasing the signal-to-noise ratio (SNR) of the system
  • The overall system bandwidth must be large enough to accommodate optimal settling of the input signal at the ADC input before the conversion starts

CFLT is chosen based upon Equation 7. CFLT is chosen to be 1 nF.

Equation 7. OPA2626 EQ_CFLT_SBOS688.gif

Connecting a 1-nF capacitor directly to the output of the OPA2626 degrades the OPA2626 phase margin and results in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used to isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To determination a suitable value for RFLT, the system designer must consider the impact upon the THD resulting from the voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well as the impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In this design example, Figure 12 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with CFLT, which in this example is equivalent to 2 × RFLT.

For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to the 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response reference guide.