SBOSAC5 December   2022 OPT3005

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
        1. 8.6.1.1 Register Descriptions
          1. 8.6.1.1.1 Result Register (offset = 00h)
          2. 8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
          3. 8.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
          4. 8.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
          5. 8.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
          6. 8.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power-Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Soldering and Handling Recommendations
      4. 9.5.4 Mechanical Drawings
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Internal Registers

The device is operated over the I2C bus with registers that contain configuration, status, and result information. All registers are 16 bits long.

There are four main registers: result, configuration, low-limit, and high-limit. There are also two ID registers: manufacturer ID and device ID. Table 8-6 lists these registers.

Table 8-6 Register Map
REGISTERADDRESS (Hex)(1)BIT 15BIT 14BIT 13BIT 12BIT 11BIT 10BIT 9BIT 8BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Result00hE3E2E1E0R11R10R9R8R7R6R5R4R3R2R1R0
Configuration01hRN3RN2RN1RN0CTM1M0OVFCRFFHFLLPOLMEFC1FC0
Low Limit02hLE3LE2LE1LE0TL11TL10TL9TL8TL7TL6TL5TL4TL3TL2TL1TL0
High Limit03hHE3HE2HE1HE0TH11TH10TH9TH8TH7TH6TH5TH4TH3TH2TH1TH0
Manufacturer ID7EhID15ID14ID13ID12ID11ID10ID9ID8ID7ID6ID5ID4ID3ID2ID1ID0
Device ID7FhDID15DID14DID13DID12DID11DID10DID9DID8DID7DID6DID5DID4DID3DID2DID1DID0
(1) Register offset and register address are used interchangeably.